公开(公告)号：US20220139769A1

公开(公告)日：2022-05-05

申请号：US17579088

申请日：2022-01-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC分类号： H01L21/762 ,  H01L21/02

摘要： Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US11164945B2

公开(公告)日：2021-11-02

申请号：US16661781

申请日：2019-10-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ta Wu ,  Kuo-Hwa Tzeng ,  Chih-Hao Wang ,  Yeur-Luen Tu ,  Chung-Yi Yu

IPC分类号： H01L29/08 ,  H01L27/12 ,  H01L29/786 ,  H01L21/762 ,  H01L29/06 ,  H01L21/84

摘要： A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.

公开(公告)号：US10157780B2

公开(公告)日：2018-12-18

申请号：US15403463

申请日：2017-01-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chii-Ming Wu ,  Cheng-Ta Wu

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L21/3115

摘要： A method of making a device includes forming an opening in a dielectric layer to expose a conductive region in a substrate. The method further includes depositing a conformal layer of dopant material along sidewalls of the opening and along a top surface of the dielectric layer. The method further includes diffusing the dopant from the conformal layer of dopant material into the dielectric layer using an anneal process.

公开(公告)号：US10109756B2

公开(公告)日：2018-10-23

申请号：US14824910

申请日：2015-08-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Chia-Shiung Tsai ,  Cheng-Ta Wu ,  Xiaomeng Chen ,  Yen-Chang Chu ,  Yeur-Luen Tu

IPC分类号： H01L31/00 ,  H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/028 ,  H01L31/109 ,  H01L27/146 ,  H01L31/105

摘要： A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.

公开(公告)号：US09697989B2

公开(公告)日：2017-07-04

申请号：US14632719

申请日：2015-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ta Wu ,  Tsung Han Wu ,  Yao-Wen Hsu ,  Lun-Kuang Tan ,  Wei-Ming You ,  Ting-Chun Wang

IPC分类号： G21K5/10 ,  H01J37/317 ,  H01J37/302 ,  H01J37/304

CPC分类号： H01J37/3172 ,  H01J37/3026 ,  H01J37/304 ,  H01J2237/2814 ,  H01J2237/2815 ,  H01J2237/2817 ,  H01J2237/30461 ,  H01J2237/30483 ,  H01J2237/31703 ,  H01J2237/3171

摘要： The present disclosure provides a method for generating a parameter pattern including: performing a plurality of measurements upon a plurality of regions on a surface of a workpiece to obtain a plurality of measured results; and deriving a parameter pattern according to the plurality of measured results by a computer; wherein the parameter pattern includes a plurality of regional parameter values corresponding to each of the plurality of regions on the surface of the workpiece. The present disclosure provides a Feed Forward semiconductor manufacturing method including: forming a layer with a desired pattern on a surface of a workpiece; deriving a control signal including a parameter pattern according to spatial dimension measurements against the layer with the desired pattern distributed over a plurality of regions of the surface of the workpiece; and performing an ion implantation on the surface of the workpiece according to the control signal.

公开(公告)号：US09406675B1

公开(公告)日：2016-08-02

申请号：US14658511

申请日：2015-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Hong-Yi Wu ,  Shiu-Ko Jangjian ,  Wei-Ming You ,  Ting-Chun Wang

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L29/788 ,  H01L27/088 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423

CPC分类号： H01L27/0886 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the substrate, forming shallow trench isolations over the substrate, and forming an oxide material over the fin structure. The method further includes forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer over the oxide material, wherein the forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer includes doping carbon in a range of from about 5E19/cm3 to about 1E22/cm3.

摘要翻译： 提供半导体结构及其形成方法。 该方法包括提供基板，形成从基板挤出的翅片结构，在基底上形成浅沟槽隔离，以及在翅片结构上形成氧化物材料。 所述方法还包括在所述氧化物材料上形成碳掺杂非晶硅层或碳掺杂多晶硅层，其中形成碳掺杂非晶硅层或碳掺杂多晶硅层包括在一定范围内掺杂碳 约5E19 / cm3至约1E22 / cm3。

公开(公告)号：US20140264493A1

公开(公告)日：2014-09-18

申请号：US13871465

申请日：2013-04-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Hung Cheng ,  Ching-Wei Tsai ,  Wen-Hsing Hsieh ,  Cheng-Ta Wu ,  Yeur-Luen Tu

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate.

摘要翻译： 半导体器件包括衬底，具有至少一个栅极顶点的栅极堆叠，栅极顶点指向栅极叠层下方的衬底中的区域。 半导体器件还包括具有朝向衬底中的区域的至少一个顶点的源结构和具有指向衬底中的区域的至少一个顶点的漏极结构。

公开(公告)号：US20240355618A1

公开(公告)日：2024-10-24

申请号：US18761373

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu ,  Chia-Ta Hsieh ,  Kuo Wei Wu ,  Yu-Chun Chang ,  Ying Ling Tseng

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L21/02359 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649

摘要： Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

公开(公告)号：US20240347377A1

公开(公告)日：2024-10-17

申请号：US18754653

申请日：2024-06-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Hung Cheng ,  Pu-Fang Chen ,  Cheng-Ta Wu ,  Po-Jung Chiang ,  Ru-Liang Lee ,  Victor Y. Lu ,  Yen-Hsiu Chen ,  Yeur-Luen Tu ,  Yu-Lung Yeh ,  Shi-Chieh Lin

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/84

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/84 ,  H01L21/26506

摘要： Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

公开(公告)号：US20240154023A1

公开(公告)日：2024-05-09

申请号：US18402971

申请日：2024-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Ta Wu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L29/6653 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/84 ,  H01L27/1203

摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC). The IC includes a pair of source/drain regions in a substrate. A gate dielectric layer is on the substrate and laterally between the source/drain regions. A gate electrode overlies the gate dielectric layer. A sidewall liner is disposed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer overlies the substrate and is on sidewalls and an upper surface of the sidewall liner. The sidewall spacer has a pair of segments respectively on opposite sides of the gate electrode. The sidewall spacer consists essentially of silicon oxycarbonitride. A dielectric constant of the sidewall spacer is greater than that of the sidewall liner.