公开(公告)号：US07351642B2

公开(公告)日：2008-04-01

申请号：US11036536

申请日：2005-01-14

申请人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

发明人： Walter Hartner ,  Joseph Page ,  Jonathan Davis

IPC分类号： H01L21/76

CPC分类号： H01L21/31055

摘要： A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.

摘要翻译： 一种用于补偿晶片上的径向不均匀性的方法和方法，包括以下步骤：在CMP工艺之后使膜周围的旋转基座的轴线上的膜的旋转厚度不均匀性居中; 将喷嘴定位在旋转处理单元中以沿着晶片的半径引导蚀刻溶液; 从喷嘴调节蚀刻溶液的流动; 调整旋转基座的旋转速度以控制蚀刻溶液的停留时间; 并协调旋转基座的旋转速度，蚀刻溶液的流动和喷嘴的定位，以最大限度地去除材料。 该方法可用于补偿STI氧化物的碗形不均匀性。 这些非均匀性在CMP过程之后得到补偿和解决。

公开(公告)号：US06316802B1

公开(公告)日：2001-11-13

申请号：US09282091

申请日：1999-03-30

申请人： Günther Schindler ,  Walter Hartner ,  Frank Hintermaier ,  Carlos Mazure-Espejo ,  Rainer Bruchhaus ,  Wolfgang Hönlein ,  Manfred Engelhardt

发明人： Günther Schindler ,  Walter Hartner ,  Frank Hintermaier ,  Carlos Mazure-Espejo ,  Rainer Bruchhaus ,  Wolfgang Hönlein ,  Manfred Engelhardt

IPC分类号： H01L27108

CPC分类号： H01L27/11502

摘要： The integrated semiconductor memory configuration has a semiconductor body in which selection transistors and storage capacitors are integrated. The storage capacitors have a dielectric layer configured between two electrodes. At least the upper electrode is constructed in a layered manner with a platinum layer, that is seated on the dielectric layer, and a thicker, base metal layer lying above the platinum layer.

摘要翻译： 集成半导体存储器配置具有集成了选择晶体管和存储电容器的半导体本体。 存储电容器具有在两个电极之间配置的电介质层。 至少上电极以分层的方式构成，铂层位于电介质层上，而较厚的贱金属层位于铂层之上。

公开(公告)号：US06051485A

公开(公告)日：2000-04-18

申请号：US66245

申请日：1998-04-24

申请人： Gunther Schindler ,  Walter Hartner ,  Dana Pitzer

发明人： Gunther Schindler ,  Walter Hartner ,  Dana Pitzer

IPC分类号： H01L21/285 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/60

摘要： A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at which the platinum-metal structure or pattern is to be produced; etching the silicon oxide layer so that the substrate surface area exposed by the opening formed in the mask is larger than the opening in the mask; applying a platinum-metal layer to the mask and the exposed substrate surface area; and removing the silicon oxide layer in an etching process, so that the platinum metal present on the mask is removed simultaneously therewith, and the platinum metal present on the substrate surface forms the platinum-metal pattern or structure.

摘要翻译： 一种在基板上制造铂金属结构或图案的方法，包括以下步骤：向基板施加氧化硅层; 在形成有铂金属结构或图案的位置处形成有开口的氧化硅层上施加掩模; 蚀刻氧化硅层，使得由形成在掩模中的开口露出的衬底表面积大于掩模中的开口; 将铂金层施加到掩模和暴露的基底表面区域; 并且在蚀刻工艺中除去氧化硅层，使得存在于掩模上的铂金属与其同时被除去，存在于衬底表面上的铂金属形成铂金属图案或结构。

公开(公告)号：US08912087B2

公开(公告)日：2014-12-16

申请号：US13563833

申请日：2012-08-01

申请人： Josef Hirtreiter ,  Walter Hartner ,  Ulrich Wachter ,  Juergen Foerster

发明人： Josef Hirtreiter ,  Walter Hartner ,  Ulrich Wachter ,  Juergen Foerster

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L21/283 ,  H01L23/00

CPC分类号： H01L21/283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/35121 ,  H01L2924/01015 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method for manufacturing a chip package is provided. The method includes: forming an electrically insulating material over a chip side; selectively removing at least part of the electrically insulating material thereby forming a trench in the electrically insulating material, depositing electrically conductive material in the trench wherein the electrically conductive material is electrically connected to at least one contact pad formed over the chip side; forming an electrically conductive structure over the electrically insulating material, wherein at least part of the electrically conductive structure is in direct physical and electrical connection with the electrically conductive material; and depositing a joining structure over the electrically conductive structure.

摘要翻译： 提供了一种制造芯片封装的方法。 该方法包括：在芯片侧上形成电绝缘材料; 选择性地去除所述电绝缘材料的至少一部分，从而在所述电绝缘材料中形成沟槽，在所述沟槽中沉积导电材料，其中所述导电材料电连接到在所述芯片侧上形成的至少一个接触焊盘; 在所述电绝缘材料上形成导电结构，其中所述导电结构的至少一部分与所述导电材料直接物理和电连接; 以及在所述导电结构上沉积接合结构。

公开(公告)号：US08637378B2

公开(公告)日：2014-01-28

申请号：US13156970

申请日：2011-06-09

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/763 ,  H01L27/105

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

摘要翻译： 半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层 半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。 掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。 隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。

公开(公告)号：US08476734B2

公开(公告)日：2013-07-02

申请号：US13156987

申请日：2011-06-09

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/763 ,  H01L27/105

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

摘要翻译： 半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层 半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。 掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。 隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。

公开(公告)号：US20110233721A1

公开(公告)日：2011-09-29

申请号：US13156987

申请日：2011-06-09

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L29/06

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

摘要翻译： 半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层 半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。 掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。 隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。

公开(公告)号：US20070018274A1

公开(公告)日：2007-01-25

申请号：US11478912

申请日：2006-06-30

申请人： Dietrich Bonart ,  Walter Hartner ,  Hermann Gruber ,  Andreas Meiser

发明人： Dietrich Bonart ,  Walter Hartner ,  Hermann Gruber ,  Andreas Meiser

IPC分类号： H01L29/00

CPC分类号： H01L27/0805 ,  H01L28/60

摘要： One aspect of the present invention relates to a semiconductor circuit arrangement and to a method for producing the latter. One aspect of the invention is that, as a result of a connecting trench structure and an isolation trench structure of a semiconductor circuit being in direct spatial proximity with respect to one another, an additional capacitor device is formed. The capacitance of said capacitor device is connected as a usable capacitance for the semiconductor circuit and is connected to the latter.

摘要翻译： 本发明的一个方面涉及一种半导体电路装置及其制造方法。 本发明的一个方面是，由于半导体电路的连接沟槽结构和隔离沟槽结构相对于彼此直接空间接近，所以形成附加的电容器器件。 所述电容器件的电容被连接作为用于半导体电路的可用电容并连接到该电容器。

公开(公告)号：US06197633B1

公开(公告)日：2001-03-06

申请号：US09281822

申请日：1999-03-30

申请人： Günther Schindler ,  Walter Hartner ,  Carlos Mazure-Espejo

发明人： Günther Schindler ,  Walter Hartner ,  Carlos Mazure-Espejo

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.

摘要翻译： 一种用于产生包括多个存储单元的存储器配置的方法，并且具有其第一电极以彼此并列的方式配置为板形的存储电容器。 这些电极通过具有不同长度的接触插塞与存储器单元的选择晶体管电接触。 优选地，第一电极延伸超过一个存储单元的单元区域。

公开(公告)号：US07982284B2

公开(公告)日：2011-07-19

申请号：US11477076

申请日：2006-06-28

申请人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

发明人： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC分类号： H01L21/763 ,  H01L27/105

CPC分类号： H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

摘要翻译： 半导体部件包括半导体本体，其中形成有：第一导电类型的衬底，布置在衬底上的第二导电类型的埋入半导体层，以及布置在埋置的第三导电类型的功能单元半导体层 半导体层，其中设置有横向彼此排列的至少两个半导体功能单元。 掩埋半导体层是至少一个半导体功能单元的一部分，半导体功能单元通过渗透功能单元半导体层，埋入半导体层和基板的隔离结构彼此电绝缘。 隔离结构包括至少一个沟槽和与衬底的导电接触，与衬底的接触通过至少一个沟槽与功能单元半导体层和掩埋层电绝缘。