公开(公告)号：US20180337142A1

公开(公告)日：2018-11-22

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Po-Han LEE ,  Wei-Chung YANG ,  Kuan-Jung WU ,  Shu-Ming CHANG

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/167 ,  H01L27/14643 ,  H01L2224/02373

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US20160211297A1

公开(公告)日：2016-07-21

申请号：US15001065

申请日：2016-01-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L27/146

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

Abstract translation: 芯片封装的制造方法包括以下步骤。 透光基板结合到晶片的第一表面，使得透光基板和晶片之间的阻挡元件覆盖晶片的导电焊盘。 蚀刻晶片背离第一表面的第二表面，使得在晶片中同时形成中空区域和选择性地与中空区域连通的沟槽。 蚀刻导电焊盘上的第一隔离层，以通过中空区域露出导电焊盘。

公开(公告)号：US20140015111A1

公开(公告)日：2014-01-16

申请号：US13941854

申请日：2013-07-15

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shih-Chin CHEN ,  Yi-Ming CHANG ,  Chien-Hui CHEN ,  Chia-Ming CHENG ,  Wei-Luen SUEN ,  Chen-Han CHIANG

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/1416 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 设置在所述基板中的装置区域; 位于半导体衬底的第一表面上的电介质层; 位于所述电介质层中并电连接到所述器件区域的多个导电焊盘; 设置在所述半导体衬底中并且从所述第二表面朝向所述第一表面延伸的至少一个对准标记。

公开(公告)号：US20130316494A1

公开(公告)日：2013-11-28

申请号：US13956487

申请日：2013-08-01

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG

IPC: H01L23/00

CPC classification number: H01L24/85 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的基板; 位于衬底上表面的钝化层; 多个导电焊盘结构，其布置在所述衬底的上表面上方，其中所述导电焊盘结构的上表面的至少部分被暴露; 从所述基板的上表面向下表面延伸的多个开口; 以及位于所述开口之间且分别与所述基板连接的多个可移动块，其中每个所述可移动块与所述导电垫结构之一电连接。

公开(公告)号：US20250054849A1

公开(公告)日：2025-02-13

申请号：US18779105

申请日：2024-07-22

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Po-Jung CHEN ,  Chia-Ming CHENG ,  Po-Shen LIN ,  Jiun-Yen LAI ,  Tsang-Yu LIU ,  Shu-Ming CHANG

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/15 ,  H01L23/528

Abstract: A chip package is provided. The chip package includes a device substrate, a first redistribution layer (RDL), a carrier base, and at least one conductive connection structure. The device substrate has at least one first through-via opening extending from the backside surface of the device substrate to the active surface of the device substrate. The first RDL is disposed on the backside surface of the device substrate and extends in the first through-via opening. The carrier base carries the device substrate, and has a first surface facing the backside surface of the device substrate and a second surface opposite the first surface. The conductive connection structure is disposed on the second surface of the carrier base and is electrically connected to the first RDL.

公开(公告)号：US20240116751A1

公开(公告)日：2024-04-11

申请号：US18480385

申请日：2023-10-03

Applicant: Xintec Inc.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG ,  Tsang Yu LIU

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0064 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0118

Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

公开(公告)号：US20230420387A1

公开(公告)日：2023-12-28

申请号：US18462414

申请日：2023-09-07

Applicant: Xintec Inc.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/528 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L23/66 ,  H01L23/5286 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/5226 ,  H01L2223/6677 ,  H01L2223/6605

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

公开(公告)号：US20220344396A1

公开(公告)日：2022-10-27

申请号：US17861011

申请日：2022-07-08

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US20210159350A1

公开(公告)日：2021-05-27

申请号：US17075544

申请日：2020-10-20

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Wei-Ming CHIEN

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/02 ,  H01L31/18

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

公开(公告)号：US20180102321A1

公开(公告)日：2018-04-12

申请号：US15724058

申请日：2017-10-03

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Po-Han LEE ,  Chia-Ming CHENG ,  Hsin-Yen LIN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00

Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.