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    Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
    21.
    发明授权
    Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same 失效
    用于制造绝缘体外延半导体（SOI）结构的结构和方法以及利用形成用于形成绝缘体材料的材料形成柔性衬底的器件

    公开(公告)号：US06693298B2

    公开(公告)日：2004-02-17

    申请号：US09908707

    申请日：2001-07-20

    申请人： Kurt W. Eisenbeiser ,  Zhiyi Yu ,  Ravindranath Droopad

    发明人： Kurt W. Eisenbeiser ,  Zhiyi Yu ,  Ravindranath Droopad

    IPC分类号： H01L2904

    CPC分类号： H01L21/7624 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532

    摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

    摘要翻译： 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 然后在容纳缓冲层上形成单晶层，使得单晶层的晶格常数与随后生长的单晶膜的晶格常数基本一致。

    Semiconductor structure exhibiting reduced leakage current and method of fabricating same
    23.
    发明授权
    Semiconductor structure exhibiting reduced leakage current and method of fabricating same 有权
    具有减小漏电流的半导体结构及其制造方法

    公开(公告)号：US07045815B2

    公开(公告)日：2006-05-16

    申请号：US10207210

    申请日：2002-07-30

    申请人： Zhiyi Yu ,  Ravindranath Droopad

    发明人： Zhiyi Yu ,  Ravindranath Droopad

    IPC分类号： H01L29/12

    CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517

    摘要： A semiconductor structure exhibiting reduced leakage current is formed of a monocrystalline substrate (101) and a strained-layer heterostructure (105). The strained-layer heterostructure has a first layer (102) formed of a first monocrystalline oxide material having a first lattice constant and a second layer (104) formed of a second monocrystalline oxide material overlying the first layer and having a second lattice constant. The second lattice constant is different from the first lattice constant. The second layer creates strain within the oxide material layers, at the interface between the first and second oxide material layers of the heterostructure, and at the interface of the substrate and the first layer, which changes the energy band offset at the interface of the substrate and the first layer.

    摘要翻译： 显示出减小的漏电流的半导体结构由单晶衬底（101）和应变层异质结构（105）形成。 应变层异质结构具有由具有第一晶格常数的第一单晶氧化物材料形成的第一层（102）和由第二单晶氧化物材料形成并具有第二晶格常数的第二单晶氧化物材料形成的第二层（104）。 第二晶格常数与第一晶格常数不同。 第二层在异质结构的第一和第二氧化物层之间的界面处以及衬底和第一层的界面处在氧化物材料层内产生应变，这改变了衬底界面处的能带偏移 和第一层。

    MOSFET STRUCTURE AND METHOD OF MANUFACTURE
    29.
    发明申请
    MOSFET STRUCTURE AND METHOD OF MANUFACTURE 有权
    MOSFET结构及其制造方法

    公开(公告)号：US20090085073A1

    公开(公告)日：2009-04-02

    申请号：US11864274

    申请日：2007-09-28

    申请人： Ravindranath Droopad ,  Matthias Passlack

    发明人： Ravindranath Droopad ,  Matthias Passlack

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28264 ,  H01L29/517

    摘要： A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.

    摘要翻译： 形成化合物半导体MOSFET结构的部分（10）的方法包括：形成化合物半导体层结构（14）和覆盖其上的氧化物层（20）。 形成化合物半导体结构（14）包括形成至少一个沟道材料（16）和覆盖至少一个沟道材料的III族富集表面终止层（18）。 形成氧化物层（20）包括形成氧化物层以覆盖III族富集表面终止层，并且包括（a）基本上一致地沉积（a（i））三元氧化物和（ （ii））比三元氧化物更复杂的氧化物和（b）使用（b（i））三元氧化物和（b（ii））中的至少一种沉积氧化物分子，其比 三元氧化物。

    High K dielectric film
    30.
    发明授权
    High K dielectric film 有权
    高K电介质膜

    公开(公告)号：US07105886B2

    公开(公告)日：2006-09-12

    申请号：US10895552

    申请日：2004-07-21

    申请人： Ravindranath Droopad

    发明人： Ravindranath Droopad

    IPC分类号： A01L29/76

    CPC分类号： H01L21/28194 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02269 ,  H01L21/28273 ,  H01L21/31604 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A dielectric layer comprised of lanthanum, lutetium, and oxygen that is formed between two conductors or a conductor and a substrate. In one embodiment, the dielectric layer is formed over the substrate without the need for an additional interfacial layer. In another embodiment, the dielectric layer is graded with respect to the lanthanum or lutetium content or in the alternative, may include aluminum. In yet another embodiment, an insulating layer is formed between the conductor or substrate and the dielectric layer or between both the conductor and substrate and the dielectric layer. The dielectric layer is preferably formed by molecular beam epitaxy, but can also be formed by atomic layer chemical vapor deposition, physical vapor deposition, organometallic chemical vapor deposition or pulsed laser deposition.

    摘要翻译： 由镧，镥和氧构成的介电层，其形成在两个导体或导体与基板之间。 在一个实施例中，介电层形成在衬底上，而不需要额外的界面层。 在另一个实施方案中，介电层相对于镧或镥含量分级，或者替代地，可以包括铝。 在另一个实施例中，在导体或衬底与电介质层之间或在导体和衬底与电介质层之间形成绝缘层。 电介质层优选通过分子束外延形成，但也可以通过原子层化学气相沉积，物理气相沉积，有机金属化学气相沉积或脉冲激光沉积形成。