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    HIGH-THROUGHPUT DEPOSITION OF A VOLTAGE-TUNABLE DIELECTRIC MATERIAL
    22.
    发明申请
    HIGH-THROUGHPUT DEPOSITION OF A VOLTAGE-TUNABLE DIELECTRIC MATERIAL 有权
    电压 - 电容材料的高通量沉积

    公开(公告)号：US20160351655A1

    公开(公告)日：2016-12-01

    申请号：US14727088

    申请日：2015-06-01

    申请人： BLACKBERRY LIMITED

    发明人： Marina ZELNER ,  Susan NAGY ,  Andrew Vladimir Claude CERVIN ,  James DiLORENZO

    IPC分类号： H01L49/02 ,  H01L21/285 ,  H01L21/288

    CPC分类号： H01L28/60 ,  C23C14/3492 ,  C23C16/40 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/2022 ,  H01L21/285 ,  H01L21/288 ,  H01L27/1281 ,  H01L28/56 ,  H01L29/4925 ,  H01L2224/4051 ,  H01L2224/4851 ,  H01L2924/00014 ,  H01L2224/37099

    摘要： High-throughput deposition of a voltage-tunable dielectric material onto a substrate comprising a conductive electrode is provided. Respective gradients in at least two grain size defining parameters of the deposition are simultaneously provided, the respective gradients occurring for a first time period thereby producing a smoothly changing columnar crystalline habit of the voltage-tunable dielectric material. When the first time period has ended, the deposition continues for a second time period where the grain size defining parameters are held constant. In particular, the smoothly changing columnar crystalline habit of the voltage-tunable dielectric material is intentionally distorted by simultaneously providing the respective gradients in the in at least two grain size defining parameters of the deposition.

    摘要翻译： 提供了将电压可调电介质材料高效地沉积到包括导电电极的基片上。 同时提供至少两个晶粒尺寸限定沉积参数的各自的梯度，在第一时间段内出现相应的梯度，从而产生电压可调介质材料的平滑变化的柱状结晶习性。 当第一时间段结束时，沉积继续进行第二时间段，其中晶粒尺寸限定参数保持恒定。 特别地，电压可调电介质材料的平滑变化的柱状结晶习性通过同时以沉积的至少两个晶粒尺寸限定参数提供各自的梯度而有意地变形。

    Methods of operating ferroelectric memory cells, and related ferroelectric memory cells
    23.
    发明授权
    Methods of operating ferroelectric memory cells, and related ferroelectric memory cells 有权
    铁电存储器单元的运行方法及相关的铁电存储单元

    公开(公告)号：US09460770B1

    公开(公告)日：2016-10-04

    申请号：US14842124

    申请日：2015-09-01

    申请人： Micron Technology, Inc.

    发明人： Steven C. Nicholes ,  Ashonita A. Chavan ,  Matthew N. Rocklein

    IPC分类号： G11C11/22 ,  H01L27/115 ,  G11C11/56 ,  G11C13/04 ,  G11C14/00

    CPC分类号： G11C11/225 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/5657 ,  G11C13/047 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

    摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

    摘要翻译： 操作铁电存储单元的方法。 该方法包括将正偏置电压和负偏置电压中的一个施加到包括上电极，底电极，顶电极和底电极之间的铁电材料的电容器和铁电存储单元之间的界面材料的铁电存储单元， 铁电材料和顶电极和底电极之一。 该方法还包括将另一个正偏置电压和负偏置电压施加到铁电存储单元以切换铁电存储单元的极化，其中负偏置电压的绝对值与正偏压的绝对值不同 电压。 还描述了铁电存储器单元。

    THIN FILM DIELECTRIC STACK
    24.
    发明申请
    THIN FILM DIELECTRIC STACK 审中-公开
    薄膜电介质堆叠

    公开(公告)号：US20160268048A1

    公开(公告)日：2016-09-15

    申请号：US14642222

    申请日：2015-03-09

    申请人： BlackBerry Limited

    发明人： Marina Zelner ,  Susan Nagy ,  Andrew Vladimir Claude Cervin

    IPC分类号： H01G4/33 ,  H01G4/012 ,  H01G4/12 ,  H01L49/02

    CPC分类号： H01G4/33 ,  H01G4/012 ,  H01G4/1227 ,  H01L28/56

    摘要： A system that incorporates teachings of the subject disclosure may include, for example, a fabricated thin film capacitor formed by depositing a first dielectric layer on a first electrode layer utilizing a first process that is performed at a first temperature, depositing a second dielectric layer on the first dielectric layer utilizing a second process that forms a randomly-oriented grain structure for the second dielectric layer, depositing a third dielectric layer on the second dielectric layer utilizing a third process that is performed at a second temperature and that forms a columnar-oriented grain structure for the third dielectric layer where the second temperature is higher than the first temperature, and depositing a second electrode layer on the third dielectric layer to form the thin film capacitor. Other embodiments are disclosed.

    摘要翻译： 结合本公开的教导的系统可以包括例如通过在第一电极层上沉积第一电介质层而形成的制造的薄膜电容器，所述第一电介质层利用在第一温度下执行的第一工艺，将第二电介质层沉积在 所述第一电介质层利用形成用于所述第二电介质层的随机取向的晶粒结构的第二工艺，利用在第二温度下进行的第三工艺，在所述第二电介质层上沉积第三电介质层，并形成柱状取向 晶体结构，其中所述第二温度高于所述第一温度，以及在所述第三电介质层上沉积第二电极层以形成所述薄膜电容器。 公开了其他实施例。

    Metal-insulator-metal stack and method for manufacturing the same
    25.
    发明授权
    Metal-insulator-metal stack and method for manufacturing the same 有权
    金属绝缘体 - 金属叠层及其制造方法

    公开(公告)号：US09431474B2

    公开(公告)日：2016-08-30

    申请号：US13705512

    申请日：2012-12-05

    申请人： IMEC

    发明人： Mihaela Ioana Popovici

    IPC分类号： B05D5/12 ,  H01L49/02 ,  H01G4/008 ,  H01L21/3205 ,  B05D7/00 ,  H01L21/02

    CPC分类号： H01L28/57 ,  B05D5/12 ,  B05D7/50 ,  H01G4/008 ,  H01L21/02 ,  H01L21/3205 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75 ,  H01L49/02

    摘要： A method for manufacturing a metal-insulator-metal (MIM) stack is described. The method includes forming a temporary stack by depositing a bottom electrode comprising at least one metal layer; depositing a dielectric comprising at least one layer of a dielectric material having a first dielectric constant value; and depositing a top electrode comprising at least one metal layer. The step of depositing the bottom and/or top electrode includes depositing a non-conductive metal oxide layer directly in contact with the dielectric; and after the step of depositing the bottom and/or top electrode's non-conductive metal oxide layer and the dielectric, subjecting the temporary stack to a stimulus, which transforms the non-conductive metal oxide into a thermodynamically stable oxide having conductive properties or into a metal, and the dielectric material into a crystalline form having a second dielectric constant value higher than the first dielectric constant value, thereby creating the final MIM stack.

    摘要翻译： 描述了金属 - 绝缘体 - 金属（MIM）堆叠的制造方法。 该方法包括通过沉积包括至少一个金属层的底部电极形成临时堆叠; 沉积包含至少一层具有第一介电常数值的电介质材料的电介质; 以及沉积包括至少一个金属层的顶部电极。 沉积底部和/或顶部电极的步骤包括直接与电介质接触地沉积非导电金属氧化物层; 并且在沉积底部和/或顶部电极的非导电金属氧化物层和电介质的步骤之后，对临时堆叠施加刺激，其将非导电金属氧化物转变成具有导电性能的热力学稳定的氧化物或者 金属和电介质材料变成具有高于第一介电常数值的第二介电常数值的结晶形式，由此形成最终的MIM堆叠。

    DEVICE COMPRISING A PLURALITY OF THIN LAYERS
    27.
    发明申请
    DEVICE COMPRISING A PLURALITY OF THIN LAYERS 审中-公开
    包含多层薄层的设备

    公开(公告)号：US20150364536A1

    公开(公告)日：2015-12-17

    申请号：US14415992

    申请日：2013-07-19

    申请人： THALES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (C.N.R.S.) ,  Universite Paris-Sud

    发明人： Manuel Bibes ,  Agnes Barthelemy

    IPC分类号： H01L49/02 ,  H01L49/00 ,  H01L27/115 ,  G11C11/22 ,  G11C11/56

    CPC分类号： H01L28/55 ,  G11C11/221 ,  G11C11/2275 ,  G11C11/5657 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/75 ,  H01L29/8615 ,  H01L49/003

    摘要： The invention relates to a device (10) including a plurality of thin layers (12, 14, 18) comprising a layer (14) formed with a polarizable ferroelectric material according to several polarization directions depending on an electric voltage applied to said layer of ferroelectric material, surrounded by a pair of conductive layers (12, 18) forming electrodes. The device of the invention comprises an intermediate layer (16) between said ferroelectric material layer (14) and one of the conductive layers (12, 18), said intermediate layer (16) consisting of a material for which the electronic properties are modified according to the direction of polarization in said adjacent ferroelectric material layout (14). The device for the invention finds particularly advantageous applications as a memory element of a non-volatile memory, as an element of a programmable logic circuit and as a microswitch.

    摘要翻译： 本发明涉及一种包括多个薄层（12,14,18）的装置（10），包括根据几个极化方向形成的可极化铁电材料的层（14），这取决于施加到所述铁电层上的电压 材料，被形成电极的一对导电层（12,18）包围。 本发明的器件包括在所述铁电材料层（14）和导电层（12,18）之一之间的中间层（16），所述中间层（16）由电子性能根据 到所述相邻的铁电材料布局（14）中的偏振方向。 用于本发明的装置作为非易失性存储器的存储元件，作为可编程逻辑电路的元件和微型开关发现特别有利的应用。

    DRAM INTERCONNECT STRUCTURE HAVING FERROELECTRIC CAPACITORS
    28.
    发明申请
    DRAM INTERCONNECT STRUCTURE HAVING FERROELECTRIC CAPACITORS 审中-公开
    具有电磁电容器的DRAM互连结构

    公开(公告)号：US20150318285A1

    公开(公告)日：2015-11-05

    申请号：US14266384

    申请日：2014-04-30

    申请人： STMicroelectronics, Inc.

    发明人： John H. Zhang

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L49/02

    CPC分类号： H01L28/56 ,  H01L21/02197 ,  H01L21/28291 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65

    摘要： An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.

    摘要翻译： 公开了一种用于集成电路中的耦合晶体管的互连结构，包括其中呈现负电容的铁电电容与介质电容器串联耦合的各种配置。 在一个实施例中，负电容器包括电介质/铁电双层。 当负电容器与传统介质电容器串联电耦合时，串联组合的行为就像一个稳定的铁电电容器，其整体电容可以通过实验测量并调谐到所需的值。 在理论上，介电电容器和负电容串联的铁电电容器的复合电容在理论上是无限的，并且在实践中非常大。 可以使用微电子互连结构内的正和负电容器的串联组合来制造高容量DRAM存储器单元。

    Method of fabricating a ferroelectric capacitor
    29.
    发明授权
    Method of fabricating a ferroelectric capacitor 有权
    制造铁电电容器的方法

    公开(公告)号：US09111944B2

    公开(公告)日：2015-08-18

    申请号：US14222904

    申请日：2014-03-24

    申请人： Cypress Semiconductor Corporation

    发明人： Shan Sun

    IPC分类号： H01L49/02 ,  H01L27/115

    CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/57

    摘要： Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top electrode formed by etching through the top electrode layer and at least partially through the ferroelectric layer. A non-conductive barrier is formed on sidewalls formed by etching through the top electrode layer and at least partially through the ferroelectric layer, and then a bottom electrode is formed by etching the bottom electrode layer so that conductive residues generated by the etching are electrically isolated from the top electrode by the non-conductive barrier.

    摘要翻译： 描述了用于铁电随机存取存储器（F-RAM）的铁电电容器及其制造方法以减少侧壁漏电。 在一个实施例中，该方法包括在衬底的表面上沉积铁电堆，其包括电耦合到延伸穿过衬底的底部电极触点的底部电极层，其间的顶部电极层和铁电层。 在铁叠层上形成硬掩模，以及通过蚀刻穿过顶部电极层并且至少部分地穿过铁电层而形成的顶部电极。 在通过蚀刻通过顶部电极层并且至少部分地穿过铁电层形成的侧壁上形成非导电屏障，然后通过蚀刻底部电极层形成底部电极，使得由蚀刻产生的导电残留物电隔离 从顶部电极通过非导电屏障。