公开(公告)号：US20140175515A1

公开(公告)日：2014-06-26

申请号：US13725546

申请日：2012-12-21

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

IPC分类号： H01L29/772 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

摘要翻译： III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。

公开(公告)号：US20140124864A1

公开(公告)日：2014-05-08

申请号：US13714353

申请日：2012-12-13

申请人： SK HYNIX INC.

发明人： Yeong Eui HONG

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/11206 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/266 ,  H01L21/28017 ,  H01L21/31105 ,  H01L23/5252 ,  H01L29/66409 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

摘要翻译： 提供半导体器件的反熔丝及其制造方法，其能够通过在特定点断开反熔丝而使反熔丝稳定地工作，并且在破裂反熔丝时稳定电流水平。 反熔丝可以包括：在半导体衬底中限定第一有源区的器件隔离层; 设置在所述第一有源区中的第一和第二接合区; 形成在所述第一接合区域上的第二有源区; 栅极绝缘层，形成在所述第一有源区和所述第二有源区上; 以及形成在栅绝缘层上的栅电极。

公开(公告)号：US07704892B2

公开(公告)日：2010-04-27

申请号：US11517087

申请日：2006-09-07

申请人： Dong-kyun Nam ,  Heon-jong Shin ,  Hyung-tae Ji

发明人： Dong-kyun Nam ,  Heon-jong Shin ,  Hyung-tae Ji

IPC分类号： H01L21/22 ,  H01L23/528

CPC分类号： H01L21/76895 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/66409 ,  H01L29/80

摘要： A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

摘要翻译： 提供具有局部互连层的半导体器件及其制造方法。 局部互连层形成在隔离层和接合层上的层间绝缘层（ILD）层中，用于覆盖半导体衬底，隔离层和栅极图案。 在本地互连层下形成具有至少一层用于防止隔离层蚀刻的蚀刻停止图案。 当形成局部互连层时，可以包括具有防止隔离层蚀刻的至少一层的蚀刻停止图案，从而防止由隔离层的蚀刻引起的漏电流，改善半导体器件的电特性，以及 提高制造半导体器件的工艺的产量。

公开(公告)号：US20070252178A1

公开(公告)日：2007-11-01

申请号：US11740728

申请日：2007-04-26

申请人： Hidekatsu ONOSE

发明人： Hidekatsu ONOSE

IPC分类号： H01L31/112

CPC分类号： H01L29/8083 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/66409 ,  H01L29/7722

摘要： The present invention can maintain a blocking state, even at a low gate bias voltage, in a diode-containing type of junction FET, and achieves a large saturation current.The junction FET includes: an n+ SiC substrate 10 as a drain layer; an n− SiC layer 11 contiguous to the drain layer as a drift layer; an n+ SiC layer 12 formed on the drift layer as a source layer; trench grooves formed ranging from the source layer to a required depth of the drift layer and part of the drift layer as a channel region; and p-type polycrystalline Si formed in the trench grooves as gate regions. The gate region at one side of the channel is electrically shorted to a source electrode to form a p− emitter of a diode.

摘要翻译： 本发明即使在低二极管的类型的结型FET中也能保持低的栅极偏置电压下的阻塞状态，并且实现了大的饱和电流。 结型FET包括：作为漏极层的n + S + SiC衬底10; 与漏极层邻接的n + SiC层11作为漂移层; 形成在漂移层上的作为源层的n + S + SiC层12; 从源极层到漂移层的所需深度和漂移层的一部分形成为沟道区的沟槽， 以及形成在沟槽中的p型多晶Si作为栅极区。 通道一侧的栅极区域与源电极电短路以形成二极管的p-O - 发射极。

公开(公告)号：US20070010090A1

公开(公告)日：2007-01-11

申请号：US11517087

申请日：2006-09-07

申请人： Dong-kyun Nam ,  Heon-jong Shin ,  Hyung tae Ji

发明人： Dong-kyun Nam ,  Heon-jong Shin ,  Hyung tae Ji

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/31116 ,  H01L21/76897 ,  H01L29/66409 ,  H01L29/80

摘要： A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

摘要翻译： 提供具有局部互连层的半导体器件及其制造方法。 局部互连层形成在隔离层和接合层上的层间绝缘层（ILD）层中，用于覆盖半导体衬底，隔离层和栅极图案。 在本地互连层下形成具有至少一层用于防止隔离层蚀刻的蚀刻停止图案。 当形成局部互连层时，可以包括具有防止隔离层蚀刻的至少一层的蚀刻停止图案，从而防止由隔离层的蚀刻引起的漏电流，改善半导体器件的电特性，以及 提高制造半导体器件的工艺的产量。

公开(公告)号：US20050179029A1

公开(公告)日：2005-08-18

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G11C13/02 ,  H01L21/336 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20050153469A1

公开(公告)日：2005-07-14

申请号：US11029842

申请日：2005-01-05

申请人： Mototaka Ochi

发明人： Mototaka Ochi

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/146 ,  H01L29/78 ,  H01L31/10 ,  G11C8/00

CPC分类号： H01L27/14643 ,  H01L21/76224 ,  H01L27/14687 ,  H01L29/66409

摘要： A method is provided for producing a solid-state imaging device in which a plurality of pixels are arranged two-dimensionally so as to form a photosensitive region, each of the pixels including a photodiode that photoelectrically converts incident light to store a signal charge and read-out elements for reading out the signal charge from the photodiode, and a vertical driving circuit for driving the plurality of pixels in the photosensitive region in a row direction, a horizontal driving circuit for driving the same in a column direction and an amplify circuit for amplifying an output signal are formed with MOS transistors. The method includes: forming an element isolation region with a STI (Shallow Trench Isolation) structure between the plurality of photodiodes and the plurality of MOS transistors; and forming a gate oxide film of the MOS transistors to have a thickness of 10 nm or less. All of heat treatment processes after formation of gates of the MOS transistors are performed at a temperature range that does not exceed 900° C. In a MOS-type solid-state imaging device having a fine structure, the occurrence of image defects can be suppressed sufficiently.

摘要翻译： 提供了一种制造固态成像装置的方法，其中多个像素被二维布置以形成光敏区域，每个像素包括光电转换入射光以存储信号电荷和读取的光电二极管 用于从光电二极管读出信号电荷的单元，以及用于驱动行方向上的感光区域中的多个像素的垂直驱动电路，用于沿列方向驱动光栅区域的水平驱动电路和放大电路 用MOS晶体管形成放大输出信号。 该方法包括：在多个光电二极管和多个MOS晶体管之间形成具有STI（浅沟槽隔离）结构的元件隔离区域; 以及形成所述MOS晶体管的栅极氧化膜以具有10nm或更小的厚度。 在形成MOS晶体管的栅极之后的所有热处理工艺都在不超过900℃的温度范围内进行。在具有精细结构的MOS型固态成像器件中，可以抑制图像缺陷的发生 充分地。

公开(公告)号：US09859394B2

公开(公告)日：2018-01-02

申请号：US15182533

申请日：2016-06-14

申请人： Agilome, Inc.

发明人： Paul Hoffman ,  Mitchell Lerner ,  Pieter van Rooyen

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/16 ,  H01L27/085 ,  H01L21/768 ,  H01L29/45 ,  C12Q1/68

CPC分类号： H01L29/66045 ,  C12Q1/6869 ,  G01N27/4145 ,  G01N27/4146 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/085 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66409 ,  H01L29/66969

摘要： Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. Accordingly, GFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis within a gated reaction chamber of the GFET based sensor.

公开(公告)号：US09806203B2

公开(公告)日：2017-10-31

申请号：US15178391

申请日：2016-06-09

申请人： Intel Corporation

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC分类号： H01L29/20 ,  H01L29/78 ,  H01L29/786 ,  H01L29/772 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/205

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

公开(公告)号：US20170125511A1

公开(公告)日：2017-05-04

申请号：US15405064

申请日：2017-01-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert ,  Junli Wang

IPC分类号： H01L49/02 ,  H01L21/28 ,  H01L27/06

CPC分类号： H01L27/0629 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/31051 ,  H01L21/32115 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/40 ,  H01L28/60 ,  H01L28/86 ,  H01L28/88 ,  H01L29/401 ,  H01L29/66409 ,  H01L29/66545

摘要： A metal-insulator-metal capacitor is provided in a replacement metal gate module having a gate cap formed on a gate. The capacitor includes a first electrode formed within a portion of the gate using a metal forming the gate. The first electrode has a horizontal component and a stack rising from at least a portion of the horizontal component. The capacitor further includes an insulator formed within a recess. The recess is formed to have a lower portion and walls rising from edges of the lower portion. The lower portion is formed on a different portion of the horizontal component than the stack. The walls are formed adjacent to a side wall of the stack and a portion of the gate cap. The capacitor also includes a second electrode formed within the recess and on the insulator.