公开(公告)号：US20230055307A1

公开(公告)日：2023-02-23

申请号：US17708281

申请日：2022-03-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： TIEH-CHIANG WU ,  Lingxin Zhu

IPC分类号： H01L29/417 ,  H01L23/532 ,  H01L23/528 ,  H01L29/40 ,  H01L21/768 ,  H01L21/3213

摘要： Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.

公开(公告)号：US20230047343A1

公开(公告)日：2023-02-16

申请号：US17734473

申请日：2022-05-02

申请人： Samsung Electronics Co., Ltd.

发明人： Doohyun LEE ,  Heonjong SHIN ,  Minchan GWAK ,  Seonbae KIM ,  Jinyoung PARK ,  Hyunho PARK

IPC分类号： H01L23/535 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

摘要： A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

公开(公告)号：US20230045689A1

公开(公告)日：2023-02-09

申请号：US17968201

申请日：2022-10-18

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Chi Lu ,  He Ren ,  Chi-I Lang ,  Ho-yung David Hwang ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/027

摘要： A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

公开(公告)号：US20230043714A1

公开(公告)日：2023-02-09

申请号：US17971807

申请日：2022-10-24

申请人： Samsung Electronics Co., Ltd.

发明人： Seung-Heon LEE ,  Munjun KIM ,  Jaekang KOH ,  Tae-Jong HAN

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/3213

摘要： Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

公开(公告)号：US20230030323A1

公开(公告)日：2023-02-02

申请号：US17949956

申请日：2022-09-21

申请人： ENTEGRIS, INC.

发明人： Atanu K. Das ,  Daniela White ,  Emanuel I. Cooper ,  Eric Hong ,  JeongYeol Yang ,  Juhee Yeo ,  Michael L. White ,  SeongJin Hong ,  SeungHyun Chae ,  Steven A. Lippy ,  WonLae Kim

IPC分类号： C23F1/38 ,  H01L21/3213

摘要： An etchant composition and method for etching molybdenum from a microelectronic device at an etch rate are described. A microelectronic device is contacted with an etchant composition for a time sufficient to at least partially remove the molybdenum. The etchant composition comprises at least one oxidizing agent, at least one oxidizing agent stabilizer, and at least one base and has a pH of from 7.5 to 13. The etchant composition selectively removes molybdenum at an etch rate of 5-200 Å/min.

公开(公告)号：US11569251B2

公开(公告)日：2023-01-31

申请号：US16535431

申请日：2019-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Te-Hsin Chiu

IPC分类号： H01L27/11526 ,  H01L29/49 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L21/265

摘要： An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

公开(公告)号：US20230026989A1

公开(公告)日：2023-01-26

申请号：US17368368

申请日：2021-07-06

申请人： International Business Machines Corporation

发明人： Jing Guo ,  Ekmini Anuja De Silva ,  Indira Seshadri ,  Jingyun Zhang ,  Su Chen Fan

IPC分类号： H01L21/8238 ,  H01L21/3213

摘要： Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.

公开(公告)号：US11557461B2

公开(公告)日：2023-01-17

申请号：US17344327

申请日：2021-06-10

申请人： Reno Technologies, Inc.

发明人： Imran Ahmed Bhutta

IPC分类号： H03H7/40 ,  H01J37/32 ,  H03H7/38 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/285

摘要： In one embodiment, an RF impedance matching network is disclosed. The matching network is coupled between an RF source having a variable frequency and a plasma chamber having a variable chamber impedance. The matching network includes a variable reactance element (VRE), and a control circuit coupled to the VRE and a sensor, the sensor configured to detect an RF parameter. To cause an impedance match between the RF source and the plasma chamber, the control circuit determines, based on the detected RF parameter and a VRE configuration, a new source frequency for the RF source. The impedance match then causes the variable frequency of the RF source to alter to the new source frequency.

公开(公告)号：US20230009688A1

公开(公告)日：2023-01-12

申请号：US17854930

申请日：2022-06-30

申请人： Tokyo Electron Limited

发明人： Dina H. Triyoso ,  Lior Huli ,  Corey Lemley ,  Robert D. Clark ,  Gerrit Leusink

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/687

摘要： A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

公开(公告)号：US11552077B2

公开(公告)日：2023-01-10

申请号：US17221401

申请日：2021-04-02

申请人： TESSERA LLC

发明人： Marc A. Bergendahl ,  Andrew M. Greene ,  Rajasekhar Venigalla

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/62 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

摘要： A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.