公开(公告)号：US08591700B2

公开(公告)日：2013-11-26

申请号：US12859766

申请日：2010-08-19

Applicant: Roy G. Gatchalian ,  Joseph Gregorio Soriano ,  Hee Cher Heng

Inventor： Roy G. Gatchalian ,  Joseph Gregorio Soriano ,  Hee Cher Heng

IPC: B05C13/00

CPC classification number: B05C13/02 ,  C23C16/4584

Abstract: The present disclosure is directed to a susceptor support that includes a hub and a plurality of arms extending radially from the hub, where each arm has a terminal end positioned away from the hub. The susceptor support also includes a plurality of elongated rectangular tips formed at the terminal end of each arm, each tip having a length and a width, wherein the length is greater than the width.

Abstract translation: 本公开涉及一种感受器支撑件，其包括毂和从轮毂径向延伸的多个臂，其中每个臂具有远离轮毂定位的终端。 基座支撑件还包括形成在每个臂的终端处的多个细长矩形尖端，每个尖端具有长度和宽度，其中该长度大于该宽度。

公开(公告)号：US08526214B2

公开(公告)日：2013-09-03

申请号：US13296628

申请日：2011-11-15

Applicant: Olivier Le Neel

Inventor： Olivier Le Neel

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US20130170169A1

公开(公告)日：2013-07-04

申请号：US13341890

申请日：2011-12-30

Applicant: KahWee GAN ,  Yaohuang HUANG

Inventor： KahWee GAN ,  Yaohuang HUANG

IPC: H05K7/02 ,  H01R43/00

CPC classification number: H01L25/03 ,  H01L21/561 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/24146 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/19103 ,  H01L2924/19104 ,  Y10T29/49117 ,  Y10T29/49204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes.

Abstract translation: 电路模块的实施例包括模块节点，第一子模块，第二子模块和导电结构。 第一子模块具有第一子模块节点，并且第二子模块设置在第一子模块上并且具有第二子模块节点。 导电结构将第一子模块节点耦合到模块节点之一，并将第二子模块节点耦合到模块节点之一。 电路模块的另一实施例包括模块节点，第一子模块，第二子模块和导电结构。 第一子模块具有第一子模块节点，第二子模块设置在第一子模块上并具有第二子模块节点。 导电结构将第一和第二子模块节点之一耦合到模块节点之一，并将第一子模块节点之一耦合到第二子模块节点之一。

公开(公告)号：US20130170164A1

公开(公告)日：2013-07-04

申请号：US13340345

申请日：2011-12-29

Applicant: Jing-En Luan ,  Hk Looi

Inventor： Jing-En Luan ,  Hk Looi

IPC: H05K7/06 ,  H05K3/30 ,  H05K1/16

CPC classification number: H05K3/305 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y02P70/613 ,  Y10T29/4913

Abstract: On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.

Abstract translation: 在其上使用粘合剂将电子或结构部件耦合到基板的电路基板上，设置粘合剂阻挡层以防止粘合剂干扰电路的操作。 可以在选定的位置提供接触垫并具有选定的形状，并将焊料沉积在垫上，然后回流以形成坝。 大坝可以是焊接到接触垫的结构，或者可以通过设备的另一种结构在其端部处支撑坝，使得在其用于容纳粘合剂的位置处，该坝不附着到基底。

公开(公告)号：US08466997B2

公开(公告)日：2013-06-18

申请号：US12651304

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H04N5/225 ,  H05K7/00 ,  H01L23/06

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package.

Abstract translation: 光学传感器封装具有在其表面上形成有再分布层的透明衬底，其包括窗口和多个导电迹线。 包括光学传感器和其表面上的多个接触端子的半导体衬底以与光学传感器直接相对的窗口面对面布置在透明衬底上，并且每个接触端子 电耦合到相应的一个导电端子。 透明基板具有比半导体基板更大的总体尺寸，使得透明基板的一个或多个边缘延伸超过半导体基板的对应边缘。 多个焊球定位在透明基板的表面上，每个焊球与相应的导电端子电接触。 焊球和半导体衬底至少部分地封装在形成在透明衬底的已被平坦化以暴露焊球上部的表面上的封装层中，作为光学传感器封装的接触焊盘。

公开(公告)号：US20130127041A1

公开(公告)日：2013-05-23

申请号：US13302602

申请日：2011-11-22

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/485 ,  B23K31/02 ,  B23K1/20

CPC classification number: H01L24/97 ,  B23K1/0016 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract translation: 提供球栅阵列引脚网格阵列转换方法。 示例性方法可以包括将多个焊球耦合到相应的多个引脚栅极阵列接触焊盘。 多个焊球中的每一个被封装在固定材料中。 多个焊球的一部分和固定材料的一部分被去除以提供多个暴露的焊球。 暴露的焊球被软化，并且多个销构件中的每一个插入软化的暴露的焊球中。 多个销构件形成销栅格阵列封装。

公开(公告)号：US20130105973A1

公开(公告)日：2013-05-02

申请号：US13287826

申请日：2011-11-02

Applicant: Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC: H01L23/485 ,  H01L21/56 ,  H01L21/58

CPC classification number: H01L23/48 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.

Abstract translation: 用于3D和PoP应用的eWLB封装包括支撑晶片上的再分配层。 半导体管芯耦合到再分配层，并且焊球也位于再分配层上。 模具和焊球被封装在模制化合物层中，其被平坦化以暴露焊球的顶部部分。 在模塑料层的平坦化表面上形成第二重分布层。 球栅阵列可以位于第二再分配层上以将半导体封装耦合到电路板，或者可以在相应的模制化合物层中添加另外的半导体管芯。 支撑晶片可以用作插入件，在这种情况下，它被处理以形成与第一再分配层电接触的TSV，并且再分配层也形成在支撑衬底的相对侧上。

公开(公告)号：US20120171774A1

公开(公告)日：2012-07-05

申请号：US13285867

申请日：2011-10-31

Applicant: Suman Cherian ,  Olivier Le Neel

Inventor： Suman Cherian ,  Olivier Le Neel

IPC: G01N27/00

CPC classification number: G01N33/48785 ,  Y02B10/70 ,  Y10T436/143333 ,  Y10T436/144444 ,  Y10T436/172307 ,  Y10T436/184 ,  Y10T436/19 ,  Y10T436/204998 ,  Y10T436/205831

Abstract: A chemical sensor is provided on a first semiconductor die. A potentiostat is provided on a second semiconductor die. An analog to digital converter and a microcontroller are provided on a third semiconductor die. The first die is configured to be connected to the second die. The second die is configured to be connected to the third die. The chemical sensor detects a chemical in the surrounding environment and outputs a signal to the analog to digital converter. The analog to digital converter converts the signal to a digital signal and outputs the digital signal to the microcontroller. The microcontroller provides a measurement of the concentration of the chemical in the surrounding environment.

Abstract translation: 化学传感器设置在第一半导体管芯上。 在第二半导体管芯上提供恒电位仪。 在第三半导体管芯上提供模数转换器和微控制器。 第一管芯被配置为连接到第二管芯。 第二管芯被配置为连接到第三管芯。 化学传感器检测周围环境中的化学物质，并向模数转换器输出信号。 模数转换器将信号转换为数字信号，并将数字信号输出到微控制器。 微控制器提供化学品在周围环境中的浓度的测量。

公开(公告)号：US20120162788A1

公开(公告)日：2012-06-28

申请号：US12980261

申请日：2010-12-28

Applicant: Jing-En LUAN ,  Junyong CHEN

Inventor： Jing-En LUAN ,  Junyong CHEN

IPC: G02B7/02

CPC classification number: G02B7/023 ,  G02B7/025

Abstract: Lens alignment apparatuses, methods and optical devices are disclosed. In accordance with various embodiments, a lens alignment apparatus may include at least one lens element positioned in a lens body. A lens alignment interface coupled to the lens element may be configured to permit the lens element to be angularly deflected relative to an axis of symmetry of the lens body. In other embodiments, a method of improving the resolution of an optical device may include translating a lens along an optical axis to maximize resolution at a first location, and determining a resolution in a second location in the imaging plane. The resolution in the second location may be improved by angularly deflecting the lens, and the position of the lens may then be fixed.

Abstract translation: 公开了透镜对准装置，方法和光学装置。 根据各种实施例，透镜对准装置可以包括定位在透镜体中的至少一个透镜元件。 耦合到透镜元件的透镜对准接口可以被配置为允许透镜元件相对于透镜主体的对称轴线成角度地偏转。 在其他实施例中，改进光学装置的分辨率的方法可以包括沿着光轴平移透镜以使第一位置处的分辨率最大化，以及确定成像平面中第二位置的分辨率。 可以通过使透镜成角度地偏转来改善第二位置中的分辨率，然后可以固定透镜的位置。

公开(公告)号：US20120153358A1

公开(公告)日：2012-06-21

申请号：US12975194

申请日：2010-12-21

Applicant: Ravi Shankar ,  Olivier Le Neel

Inventor： Ravi Shankar ,  Olivier Le Neel

IPC: H01L23/367 ,  H01L21/46

CPC classification number: H01L23/522 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient.

Abstract translation: 所公开的实施例的热能传递技术利用无源热能传递技术来减少在电路级别被捕获的热能的不期望的副作用。 捕获的热能可以通过具有导热结构或可以作为标准集成电路工艺的一部分产生的元件的电路传输。 在电路级别实现的热能的局部和被动去除，而不仅仅是在封装级别更有效和更有效。