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    Single mask technique for making positive and negative micromachined features on a substrate
    331.
    发明申请
    Single mask technique for making positive and negative micromachined features on a substrate 有权
    用于在衬底上制造正面和负面微加工特征的单面技术

    公开(公告)号：US20010050266A1

    公开(公告)日：2001-12-13

    申请号：US09847798

    申请日：2001-05-02

    Inventor： David W. Sherrer ,  Gregory A. Ten Eyck ,  Dan A. Steinberg ,  Neal Ricks

    IPC: B29D011/00 ,  G02B006/00

    CPC classification number: B81C1/00126 ,  B81B2203/0384 ,  B81C1/00428 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0178 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/423 ,  G02B2006/12176

    Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the positive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.

    Abstract translation: 用于制造具有正特征（从器件表面向上延伸）和负特征（延伸到器件表面）的微加工器件（例如，微光学基座）的方法。 本技术根据单个掩模步骤定位正特征和负特征。 在一个实施例中，在SOI晶片的器件层的顶部上形成硬掩模。 然后，RIE用于垂直蚀刻到蚀刻停止层，形成阳性特征。 然后，正面特征被掩蔽，并且金属或硬掩模沉积在蚀刻停止层的暴露区域上。 然后，去除器件层的部分，留下图案化的金属层在蚀刻停止层上。 然后，在曝光区域中去除蚀刻停止层，露出手柄层。 然后，在曝光区域中蚀刻手柄层以形成负面特征。

    Process for manufacture of micro electromechanical devices having high electrical isolation
    332.
    发明授权
    Process for manufacture of micro electromechanical devices having high electrical isolation 失效

    公开(公告)号：US6159385A

    公开(公告)日：2000-12-12

    申请号：US75008

    申请日：1998-05-08

    Applicant: Jun J. Yao ,  Robert J. Anderson

    Inventor： Jun J. Yao ,  Robert J. Anderson

    IPC: B81C1/00 ,  B81B3/00 ,  H01L27/12 ,  H01P11/00 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  H01L21/00

    CPC classification number: B81C1/00484 ,  B81B2203/0118 ,  B81C2201/0108 ,  B81C2201/014 ,  B81C2201/019

    Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon--silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques. A second patterning then follows to pattern the silicon dioxide layer and an oxygen plasma etch is performed to undercut the epoxy film and to release the silicon MEM component. This two-mask process provides single crystal silicon MEMs with electrically isolated MEM component. Retaining silicon dioxide insulating material in selected areas mechanically supports the MEM component.

    Semiconductor device with force and/or acceleration sensor
    335.
    发明授权
    Semiconductor device with force and/or acceleration sensor 失效
    具有力和/或加速度传感器的半导体器件

    公开(公告)号：US5554875A

    公开(公告)日：1996-09-10

    申请号：US486156

    申请日：1995-06-07

    Applicant: Siegbert Hartauer

    Inventor： Siegbert Hartauer

    IPC: B81B3/00 ,  G01L1/18 ,  G01P15/08 ,  G01P15/12 ,  G01P15/125 ,  H01L29/82

    CPC classification number: B81C1/00246 ,  G01L1/18 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2203/0728 ,  B81C2203/0735

    Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).

    Abstract translation: 一种具有力和/或加速度传感器（12）的半导体器件，其具有响应于待测量的相应量的弹簧质量系统（14,16），并且其质量（16）经由至少一个弹性支撑元件（ 14）在半导体衬底（20）上。 半导体衬底（20）和弹簧质量系统（14,16）是具有IC兼容结构的单晶半导体晶体（10）的组成部分。 通过各向异性半导体蚀刻制造弹簧质量体系（12）的三维结构形式，作为蚀刻停止装置的半导体层布置的限定的P / N结，以更具体地形成允许相应的间隙（22） 质量块（16）和半导体衬底（20）之间的质量块（16）的移动。

    Etch control seal for dissolved wafer process
    336.
    发明授权
    Etch control seal for dissolved wafer process 失效
    用于溶解晶片工艺的蚀刻控制密封

    公开(公告)号：US5509974A

    公开(公告)日：1996-04-23

    申请号：US434153

    申请日：1995-05-02

    Applicant: Kenneth M. Hays

    Inventor： Kenneth M. Hays

    IPC: C23F1/00 ,  B81C1/00 ,  G01L9/00 ,  H01L21/306 ,  H03H3/007 ,  H01L29/12

    CPC classification number: G01L9/0019 ,  B81C1/00801 ,  H03H3/007 ,  B81C2201/0136 ,  B81C2201/014 ,  Y10S148/012

    Abstract: A dissolved wafer process is modified by providing an etch control seal around the perimeter of an etch resistant microstructure, such as a micromechanical or microelectromechanical device, formed on a first substrate. The microstructure is defined and shaped by a surrounding trench in the first substrate. Selected areas of the microstructure and the first substrate are bonded to an etch resistant second substrate. The selected bonding areas may comprise raised areas of the first substrate, or raised areas of the second substrate corresponding to the selected bonding areas of the first substrate. A bonded area forming a ring extending around the perimeter of the microstructure and its defining trench forms an etch control seal. The first substrate of the bonded assembly is dissolved in a selective etch so that the etch resistant microstructure remains attached to the second substrate only at the bonded areas. The etch control seal reduces exposure of the microstructure to the etch by preventing the etch from contacting the microstructure until the etch leaks through the dissolving floor of the trench. This occurs only during the final stages of the wafer dissolution step, thus minimizing exposure of the microstructure to the damaging effects of the etch.

    Abstract translation: 通过在第一衬底上形成的耐蚀刻微结构（例如微机电或微机电装置）的周边周围提供蚀刻控制密封来改变溶解的晶片工艺。 微结构由第一衬底中的周围沟槽限定和成形。 将微结构和第一衬底的选定区域结合到耐蚀刻的第二衬底上。 所选择的结合区域可以包括第一衬底的凸起区域或者对应于第一衬底的所选择的结合区域的第二衬底的凸起区域。 形成围绕微结构周边延伸的环的结合区及其限定沟槽形成蚀刻控制密封。 粘合组件的第一衬底被溶解在选择性蚀刻中，使得耐蚀刻微结构仅在接合区域处附着到第二衬底。 蚀刻控制密封件通过防止蚀刻与微结构接触直到蚀刻泄漏通过沟槽的溶解底板来减少微结构暴露于蚀刻。 这仅发生在晶片溶解步骤的最后阶段期间，从而最小化微观结构暴露于蚀刻的破坏作用。

    Process for making semiconductor acceleration sensor having anti-etching layer
    337.
    发明授权
    Process for making semiconductor acceleration sensor having anti-etching layer 失效
    具有防腐蚀层的半导体加速度传感器的制造方法

    公开(公告)号：US5395802A

    公开(公告)日：1995-03-07

    申请号：US37335

    申请日：1993-03-26

    Applicant: Shigeyuki Kiyota ,  Hideo Muro

    Inventor： Shigeyuki Kiyota ,  Hideo Muro

    IPC: B81B3/00 ,  G01P15/08 ,  G01P15/12 ,  H01L29/84 ,  H01L21/465

    CPC classification number: B81C1/00666 ,  B81C1/00595 ,  G01P15/0802 ,  G01P15/123 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/0177 ,  G01P2015/0828 ,  Y10S438/924

    Abstract: A semiconductor acceleration transducer is fabricated so that the semiconductor beam and the piezoelectric transducing element are accurately positioned relative to each other, and the impact resistance is improved. The fabrication process comprises a wafer preparing step for forming a buried layer between a substrate of a first conductivity type and an epitaxial layer of a second conductivity type, a doping step for forming a diffusion region of the first conductivity type in the epitaxial layer, and an etching step for removing unwanted portions of the substrate and the diffusion region from the bottom of the substrate to shape the beam supporting portion serving as a seismic mass. The buried layer is formed at such a position that the shape and position of the beam is determined by the buried layer. The buried layer may be a second conductivity type layer to determine the contour of the beam by stopping the etching process or may be a first conductivity type layer which is etched away to determine the contour of the beam with its diffusion contour.

    Abstract translation: 制造半导体加速度传感器，使得半导体束和压电换能元件相对于彼此精确地定位，并且提高了抗冲击性。 制造工艺包括用于在第一导电类型的衬底和第二导电类型的外延层之间形成掩埋层的晶片准备步骤，用于在外延层中形成第一导电类型的扩散区域的掺杂步骤，以及 蚀刻步骤，用于从衬底的底部除去衬底和扩散区的不需要的部分，以形成用作抗震质量的梁支撑部分。 掩埋层形成在这样的位置，即由掩埋层决定光束的形状和位置。 掩埋层可以是第二导电类型层，以通过停止蚀刻工艺来确定光束的轮廓，或者可以是蚀刻掉的第一导电类型层，以确定具有其扩散轮廓的光束的轮廓。

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