公开(公告)号：US20230353154A1

公开(公告)日：2023-11-02

申请号：US17733934

申请日：2022-04-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois LINK ,  Mark WALLIS ,  Joran PANTEL

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

公开(公告)号：US20230325336A1

公开(公告)日：2023-10-12

申请号：US18133214

申请日：2023-04-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas SAUX ,  Sebastien METZGER ,  Herve CASSAGNES

IPC: G06F13/40 ,  G06F1/24 ,  G06F1/10

CPC classification number: G06F13/405 ,  G06F1/24 ,  G06F1/10 ,  G06F2213/0038

Abstract: The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.

公开(公告)号：US11784564B2

公开(公告)日：2023-10-10

申请号：US16933277

申请日：2020-07-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Michel Cuenca ,  Sebastien Ortet

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/088

CPC classification number: H02M3/158 ,  H02M1/0022 ,  H02M1/0032 ,  H02M1/088

Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.

公开(公告)号：US11765572B2

公开(公告)日：2023-09-19

申请号：US17122782

申请日：2020-12-15

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Alexandre Tramoni ,  Pierre Rizzo ,  Olivier Van Nieuwenhuyze

IPC: H04W8/22 ,  H04W4/029 ,  H04W4/80

CPC classification number: H04W8/22 ,  H04W4/029 ,  H04W4/80

Abstract: A method of configuration of a mobile terminal including a near-field communication device is provided. The method includes determining the geographic position of the mobile terminal. The method further includes selecting, from a configuration table stored in an internal memory of the mobile terminal, a set of one or a plurality of configuration parameters of the near-field communication device according to the geographic position, and applying a selected set of parameters to the near-field communication device.

公开(公告)号：US11764830B2

公开(公告)日：2023-09-19

申请号：US17499371

申请日：2021-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni

IPC: H04B5/00

CPC classification number: H04B5/0025 ,  H04B5/0031 ,  H04B5/0037

Abstract: An embodiment of the present description concerns a method wherein a time of beginning of a periodic step of activation of a near-field communication circuit of a first device, charged in near field by a second device, is adjusted according to a frequency of an electromagnetic field emitted by the second device.

公开(公告)号：US20230263082A1

公开(公告)日：2023-08-17

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8265 ,  H10N70/8413 ,  G11C2013/008

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US11721773B2

公开(公告)日：2023-08-08

申请号：US17366585

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Brice Arrazat ,  Julien Delalleau ,  Joel Metz

IPC: H01L21/00 ,  H01L29/94 ,  H01L21/28 ,  H01L21/265 ,  H01L49/02 ,  H01L29/423 ,  H01L29/788 ,  H10B41/35

CPC classification number: H01L29/945 ,  H01L21/2652 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/4236 ,  H01L29/788 ,  H10B41/35

Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.

公开(公告)号：US11721646B2

公开(公告)日：2023-08-08

申请号：US17159698

申请日：2021-01-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/10 ,  H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01

CPC classification number: H01L23/573 ,  G04F1/005 ,  H01L21/705 ,  H01L27/013 ,  H01L27/101

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US11715705B2

公开(公告)日：2023-08-01

申请号：US16932082

申请日：2020-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35 ,  H01L23/00 ,  G06F21/87

CPC classification number: H01L23/573 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H01L23/576 ,  H01L29/7883 ,  H10B41/35 ,  G06F21/87

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20230238272A1

公开(公告)日：2023-07-27

申请号：US18127751

申请日：2023-03-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/31116 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.