公开(公告)号：US20150116874A1

公开(公告)日：2015-04-30

申请号：US14521624

申请日：2014-10-23

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Greca Jean Charles ,  Bertrand Rivet

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/04 ,  H01L27/0248

Abstract: An overvoltage protection device uses a varistor coupled in series with a switch between two terminals provided for connection to a circuit device or element to be protected. A control circuit controls actuation of the switch in response to sensing voltage at or between the two terminals in excess of a first threshold. The first threshold is less than a clipping voltage of the varistor but in excess of a supply voltage for the circuit device or element. The control circuit further controls detactuation of the switch based, for example, on elapsed time from actuation or current flow.

Abstract translation: 过压保护装置使用与两个端子之间的开关串联耦合的压敏电阻器，用于连接到要保护的电路装置或元件。 控制电路响应于在两个端子之间或之间的感测电压超过第一阈值来控制开关的致动。 第一阈值小于压敏电阻的限幅电压，但超过电路装置或元件的电源电压。 控制电路还基于例如从致动或电流流动的经过时间来控制开关的去动。

公开(公告)号：US08994283B2

公开(公告)日：2015-03-31

申请号：US14032561

申请日：2013-09-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Laurent Gonthier ,  Antoine Passal

IPC: H05B33/08 ,  H05B39/04

CPC classification number: H05B33/0818 ,  H05B33/0815 ,  H05B39/044 ,  Y02B20/19 ,  Y02B20/348

Abstract: A circuit capable of receiving, in series with at least one light-emitting diode, a rectified A.C. voltage, comprising: a first gate turn-off thyristor connected to first and second terminals of the circuit; and a control circuit for turning off the first thyristor when the voltage between the first and second terminals exceeds a threshold.

Abstract translation: 一种能够与至少一个发光二极管串联接收整流的交流电压的电路，包括：连接到电路的第一和第二端子的第一栅极截止晶闸管; 以及用于当第一和第二端子之间的电压超过阈值时关闭第一晶闸管的控制电路。

公开(公告)号：US20150084094A1

公开(公告)日：2015-03-26

申请号：US14494692

申请日：2014-09-24

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/74 ,  H01L21/322 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L21/2807 ,  H01L21/306 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/32 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66363 ,  H01L29/66545 ,  H01L29/7408

Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.

Abstract translation: 垂直结构的SCR型分量具有形成在第二导电类型的硅层中的形成在第一导电类型的硅区上的主上电极。 在硅层的材料与上电极接触的第一区域中，硅区被中断，并且在硅层和主上电极之间延伸的第二区填充有电阻性多孔硅，进一步中断。

公开(公告)号：US20150064881A1

公开(公告)日：2015-03-05

申请号：US14464158

申请日：2014-08-20

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Arnaud YVON

IPC: H01L21/306 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/0661 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/30625 ,  H01L21/3228 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66212 ,  H01L29/872

Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.

Abstract translation: 一种用于处理第一导电类型的掺杂氮化镓衬底的方法，其具有出现在其表面的至少一个侧面上的位错。 该方法可以包括：a）在每个错位出现的地方形成从所述至少一个表面延伸到所述基底中的凹部; 以及b）用所述第二导电类型的掺杂氮化镓填充所述凹部。

公开(公告)号：US20150064567A1

公开(公告)日：2015-03-05

申请号：US14470827

申请日：2014-08-27

Applicant: STMicroelectronics (Tours) SAS

Inventor： Mohamed BOUFNICHEL ,  Jean-Christophe HOUDBERT

IPC: H01M4/38 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/04

CPC classification number: H01M4/386 ,  C09K13/00 ,  H01L21/3065 ,  H01L31/0236 ,  H01L31/02363 ,  H01M4/049 ,  H01M4/134 ,  H01M4/1395 ,  H01M2004/021 ,  H01M2004/027

Abstract: A method for forming a rough silicon wafer including the successive steps of: performing a plasma etching of a surface of the wafer in conditions suitable to obtain a rough structure, and performing two successive ion milling steps, one at an incidence in the range of 0 to 10°, the other at an incidence in the range of 40 to 60° relative to the normal to the wafer.

Abstract translation: 一种用于形成粗硅晶片的方法，包括以下连续步骤：在适于获得粗糙结构的条件下进行晶片表面的等离子体蚀刻，并进行两个连续的离子研磨步骤，一个在0的范围内 至10°，另一个相对于晶片的法线入射在40至60°的范围内。

公开(公告)号：US08963584B2

公开(公告)日：2015-02-24

申请号：US13932812

申请日：2013-07-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Martial Boulin

IPC: H03K5/153

CPC classification number: H03K19/017509 ,  H03K17/96

Abstract: A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train.

Abstract translation: 一种用于将传感器的状态转换为由电子电路解释的信号的电路，包括：输入端子相对于参考电平的电压电平的比较器，所述传感器旨在连接在应用的端子之间 第一电源电压和输入端; 所述输入端和地之间的限流元件; 以及与电流源串联并且由脉冲串控制的开关元件。

公开(公告)号：US20140062422A1

公开(公告)日：2014-03-06

申请号：US14013802

申请日：2013-08-29

Applicant: STMicroelectronics (TOURS) SAS

Inventor： Laurent Gonthier ,  Antoine Passal

IPC: H02J7/00

CPC classification number: H02J7/0052 ,  E06B3/22 ,  E06B3/26305 ,  E06B3/26345 ,  E06B3/267 ,  E06B3/822 ,  E06B2003/26312 ,  E06B2003/26316 ,  E06B2003/7076 ,  E06B2003/7082 ,  Y02A30/252 ,  Y02B80/28

Abstract: A circuit can be used for charging a capacitor with an AC voltage. In one embodiment, the circuit includes a capacitor coupled to be charged with the AC voltage. An adjustment is configured to adjust a capacitor charge speed according to a value of the AC voltage. The adjustment circuit includes at least one bipolar transistor coupled to receive a voltage at a base of the bipolar transistor. The voltage is a function of the value of the AC voltage.

Abstract translation: 电路可用于对具有交流电压的电容器充电。 在一个实施例中，电路包括耦合以对AC电压充电的电容器。 调整配置为根据交流电压的值调整电容器充电速度。 调节电路包括耦合以接收双极晶体管的基极处的电压的至少一个双极晶体管。 电压是交流电压值的函数。

公开(公告)号：US20140038028A1

公开(公告)日：2014-02-06

申请号：US13957518

申请日：2013-08-02

Applicant: STMicroelectronics (Tours) SAS

Inventor： Dominique Genard

IPC: H01M10/04

CPC classification number: H01M10/0436 ,  H01M4/0423 ,  H01M10/0525 ,  H01M10/0585 ,  Y02E60/122 ,  Y02P70/54

Abstract: A method for manufacturing a lithium-ion type battery including the steps of forming in a substrate a recess having lateral walls having a re-entrant profile; depositing, by successive non-conformal physical vapor depositions, a stack of the different layers forming a lithium-ion battery, this stack having a thickness smaller than the depth of the recess; depositing on the structure a filling layer filling the space remaining in the recess; and planarizing the structure to expose the upper surface of the stack.

Abstract translation: 一种锂离子型电池的制造方法，其特征在于，在基板上形成具有侧壁的具有凹凸轮廓的凹部的工序; 通过连续的非保形物理气相沉积沉积形成锂离子电池的不同层的堆叠，该堆叠的厚度小于凹部的深度; 在所述结构上沉积填充剩余在所述凹部中的空间的填充层; 并平坦化结构以暴露堆叠的上表面。

公开(公告)号：US20140036399A1

公开(公告)日：2014-02-06

申请号：US13955112

申请日：2013-07-31

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory ,  Eric Laconde

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for protecting an integrated circuit against overvoltages, the device being formed inside and on top of a semiconductor substrate of a first conductivity type and including: a capacitor including a well of the second conductivity type penetrating into the substrate and trenches with insulated walls formed in the well and filled with a conductive material; and a zener diode formed by the junction between the substrate and the well.

Abstract translation: 一种用于保护集成电路免受过电压的装置，该装置形成在第一导电类型的半导体衬底的内部和顶部，并且包括：电容器，包括穿透到衬底中的第二导电类型的阱和形成有绝缘壁的沟槽 在井中充满导电材料; 以及由衬底和阱之间的接合部形成的齐纳二极管。

公开(公告)号：US20130299943A1

公开(公告)日：2013-11-14

申请号：US13938593

申请日：2013-07-10

Applicant: STMicroelectronics(Tours) SAS ,  Mitsubishi Materials Corporation

Inventor： Hideaki Sakurai ,  Toshiaki Watanabe ,  Nobuyuki Soyama ,  Guillaume Guegan

IPC: H01L49/02

CPC classification number: H01L28/60 ,  B82Y30/00 ,  C04B35/4682 ,  C04B2235/3213 ,  C04B2235/441 ,  C04B2235/781 ,  C04B2235/785 ,  C04B2235/787 ,  H01G4/01 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/02282 ,  H01L28/55 ,  H01L28/65

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract translation: 薄膜电容器的特征在于形成下电极，将组合物涂覆在下电极上，而不施加温度大于300℃的退火工艺，在环境温度至500℃的范围内的预定温度下干燥 并在500〜800℃的范围内的预定温度下煅烧并高于干燥温度。 从涂覆到煅烧的过程进行从涂覆到煅烧一次或至少两次的过程，或者从涂覆到干燥的过程进行至少两次，然后进行一次煅烧。 在第一次煅烧后形成的电介质薄膜的厚度为20〜600nm。 初始煅烧步骤后形成的下部电极的厚度与电介质薄膜的厚度之比（下部电极的厚度/电介质薄膜的厚度）优选在0.10〜15.0的范围内。