公开(公告)号：US09825632B1

公开(公告)日：2017-11-21

申请号：US15228981

申请日：2016-08-04

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Michael J. Hart ,  Praful Jain ,  Robert I. Fu

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/00315 ,  H03K19/17728 ,  H03K19/1776

Abstract: A circuit for preventing multi-bit upsets induced by single event transients is described. The circuit comprises a clock generator configured to generate a first clock signal and a second clock signal; a first memory element configured to receive a first input signal and generate a first output signal, the first memory element having a first clock input configured to receive the first clock signal; and a second memory element configured to receive the first output signal and generate a second output signal, the second memory element having a second clock input configured to receive the second clock signal; wherein the first clock signal is the same as the second clock signal. A method of preventing multi-bit upsets induced by single event transients is also described.

公开(公告)号：US09811618B1

公开(公告)日：2017-11-07

申请号：US13788189

申请日：2013-03-07

Applicant: Xilinx, Inc.

Inventor： Umang Parekh ,  Arvind Sundararajan ,  Sandeep Dutta

IPC: G06F17/50 ,  G06F15/78

CPC classification number: G06F17/5036 ,  G06F15/7867 ,  G06F17/5054

Abstract: A method is provided for simulating a program executable by a processor and a circuit design configured to communicate with the processor. A processor on a programmable IC is configured to execute the program. Programmable resources on the programmable IC are configured to implement a plurality of interface circuits. Each of the interface circuits is configured to communicate data between the processor and a simulation environment using a respective communication protocol. The interface circuits that uses a communication protocol used by the circuit design is enabled and other ones of the interface circuits are disabled. The circuit design is simulated in a simulation environment coupled to the programmable IC. During the simulating, the program is executed on the processor and data is communicated between the processor and the computing platform using the determined one of the plurality of interface circuits.

公开(公告)号：US09793899B1

公开(公告)日：2017-10-17

申请号：US15382385

申请日：2016-12-16

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Jue Arver ,  Michael J. Hart ,  John K. Jennings

IPC: H03K19/003 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/0033

Abstract: The disclosed IC includes a load circuit and a temperature sensor circuit. The temperature sensor circuit measures temperature of the IC and stores temperature data in a register. An SEL mitigation circuit monitors the IC for a temperature change indicative of an SEL. A temperature change greater than a threshold over a time interval is indicative of an SEL. The SEL mitigation circuit is configured to reduce voltage applied to the IC to a voltage level that clears an SEL in the IC in response to a temperature change exceeding the threshold and to increase voltage applied to the load circuit after the reduction in voltage.

公开(公告)号：US09773543B1

公开(公告)日：2017-09-26

申请号：US15253415

申请日：2016-08-31

Applicant: Xilinx, Inc.

Inventor： Austin S. Tavares ,  Maria George

IPC: G11C5/06 ,  G11C11/408 ,  G11C11/4072

CPC classification number: G11C11/408 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C8/12 ,  G11C11/4072 ,  G11C2207/105

Abstract: Methods and apparatus are described for pinning out multiple memory devices using shared conductors therebetween and providing multiple chip select signals to indicate to which of the memory devices address signals on the shared conductors apply. In the case of a clamshell configuration with a top memory device having a corresponding bottom memory device and shared vias coupled therebetween, sharing two address signals for each shared via in this manner reduces the total number of vias used, thereby reducing routing congestion and enabling the addition of ground vias around the shared vias to reduce crosstalk for the address signals.

公开(公告)号：US09773083B1

公开(公告)日：2017-09-26

申请号：US15069598

申请日：2016-03-14

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F2217/84

Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

公开(公告)号：US09755649B1

公开(公告)日：2017-09-05

申请号：US14617424

申请日：2015-02-09

Applicant: Xilinx, Inc.

Inventor： Richa Singhal ,  Edmond Jordan ,  Ahmad R. Ansari

IPC: H03K19/177

CPC classification number: H03K19/17768

Abstract: A method for protecting an integrated circuit device against security violations includes monitoring a component of the integrated circuit device for security violations. A security violation of the component of the integrated circuit device is then identified. The component of the integrated circuit device is then internally destroyed in response to the identified security violation by providing current to the component beyond a tolerable limit of the component.

公开(公告)号：US09755600B1

公开(公告)日：2017-09-05

申请号：US15049963

申请日：2016-02-22

Applicant: Xilinx, Inc.

Inventor： Didem Z. Turker Melek ,  Parag Upadhyaya ,  Kun-Yung Chang

IPC: H03G3/30 ,  H03F1/02 ,  H03F3/16 ,  H04B1/12

CPC classification number: H03G3/3036 ,  H03F1/0205 ,  H03F1/0211 ,  H03F3/16 ,  H03F3/45197 ,  H03F2200/555 ,  H03F2203/45492 ,  H03G1/0029 ,  H03G1/0088 ,  H03G3/301 ,  H04B1/123 ,  H04L25/03885

Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

公开(公告)号：US09742380B1

公开(公告)日：2017-08-22

申请号：US15170797

申请日：2016-06-01

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Parag Upadhyaya ,  Adebabay M. Bekele

IPC: H03L7/06 ,  H03K3/013 ,  H03K5/04 ,  H03K7/08 ,  H03L7/18 ,  H03L7/197 ,  H03L7/093 ,  H03L7/091 ,  H03L7/089

CPC classification number: H03K3/013 ,  H03K5/04 ,  H03K7/08 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/091 ,  H03L7/093 ,  H03L7/18 ,  H03L7/1974

Abstract: An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.

公开(公告)号：US09734032B1

公开(公告)日：2017-08-15

申请号：US14500374

申请日：2014-09-29

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad

IPC: G06F11/263 ,  H03K19/177 ,  H03K19/007

CPC classification number: G06F11/263 ,  G06F11/27 ,  H03K19/007 ,  H03K19/1776 ,  H03K19/17764

Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system is configured to operate a hardware portion of the user design. The processing sub-system configured to execute a software portion of the user design. The safety sub-system is configured to perform a set of operations to detect errors in the programmable IC. The first set of operations writes to at least one of a set of registers using a write macro function. In response to writing to the register with the write macro function, a list of registers stored in the memory is updated to include the register. Registers included in the list of registers are tested to determine whether or not an upset has occurred.

公开(公告)号：US20170220509A1

公开(公告)日：2017-08-03

申请号：US15013696

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Ivo Bolsens

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4031

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.