中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

724 records (took 0.193 seconds)

    3D semiconductor device and structure
    371.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10825779B2

    公开(公告)日：2020-11-03

    申请号：US16907234

    申请日：2020-06-20

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach

    IPC: H01L23/02 ,  H01L21/00 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065

    Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

    3D semiconductor device and structure
    372.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10651054B2

    公开(公告)日：2020-05-12

    申请号：US16115519

    申请日：2018-08-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

    IPC: H01L21/48 ,  H01L23/498 ,  H01L27/092 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522 ,  H01L23/367 ,  H01L25/00 ,  H01L27/098 ,  H01L23/373 ,  H01L23/50 ,  H01L21/8238

    Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

    3D semiconductor device and structure
    377.
    发明授权
    3D semiconductor device and structure 有权

    公开(公告)号：US10157909B2

    公开(公告)日：2018-12-18

    申请号：US15862616

    申请日：2018-01-04

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

    IPC: H01L27/06 ,  H01L29/78

    Abstract: A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.

    3D Semiconductor Device and Structure
    380.
    发明申请
    3D Semiconductor Device and Structure 审中-公开

    公开(公告)号：US20180269229A1

    公开(公告)日：2018-09-20

    申请号：US15761426

    申请日：2016-09-21

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H01L27/118

    Abstract: A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

Patent Agency Ranking