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31.发明申请Memory System and Method for Adaptive Auto-Sleep and Background Operations 审中-公开用于自适应自动睡眠和后台操作的记忆系统和方法公开(公告)号：US20170024002A1
公开(公告)日：2017-01-26
申请号：US14803732
申请日：2015-07-20
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3225 , G06F1/3228 , G06F1/3275 , Y02D10/14
摘要： A memory system and method are provided for adaptive auto-sleep and background operations. In one embodiment, a controller of a memory system measures an amount of time between when the memory completes an operation and when the controller receives a command to perform another operation in the memory. The controller adjusts a time period after which the controller enters an auto-sleep mode and/or starts a background operation based on the measured amount of time. Other embodiments are disclosed.
摘要翻译： 提供了一种用于自适应自动睡眠和后台操作的存储器系统和方法。 在一个实施例中，存储器系统的控制器测量存储器完成操作之间和控制器接收到在存储器中执行另一操作的命令之间的时间量。 控制器调整控制器进入自动睡眠模式的时间段和/或基于测量的时间量开始后台操作。 公开了其他实施例。
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公开(公告)号：US20160372200A1
公开(公告)日：2016-12-22
申请号：US15184939
申请日：2016-06-16
发明人： Yen-Lung Li , Jong Yuh , Jonathan Huynh , Tai-Yuan Tseng , Kwang-Ho Kim , Qui Nguyen
CPC分类号： G11C16/08 , G11C7/04 , G11C16/0483 , G11C16/26 , G11C16/3459
摘要： Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.
摘要翻译： 描述了用于减少用于感测存储在多个存储器单元内的数据状态的感测时间的系统和方法。 在一些情况下，可以延迟连接到多个存储器单元的字线的斜坡，直到与多个存储器单元的特定数目的擦除存储单元相对应的阈值电流已经被满足或超过。 可以将阈值电流与对应于已经被感测为处于导通状态的多个存储器单元中的第一组存储器单元相对应的第一组检测电流的总和进行比较，同时字线被设置为电压电平 用于感测擦除的存储单元。 可以基于芯片温度和/或在先前感测操作期间发生的特定数量的位错误来设置阈值电流。
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公开(公告)号：US20160372160A1
公开(公告)日：2016-12-22
申请号：US14757780
申请日：2015-12-23
发明人： Joshua Lehmann , Gadi Vishne , David Haliva , Eran Erez
IPC分类号： G11C5/14
摘要： A memory system and method for power management are disclosed. In one embodiment, a memory system maintains a variable credit value indicating an amount of power currently available for memory operations in the memory system, the variable credit value having an upper limit that reflects a maximum power limit for the memory system. The memory system receives a command to perform a memory operation, wherein a plurality of resources are required to perform the memory operation, each resource being associated with a credit value. Prior to performing the memory operation, the memory system checks whether the variable credit value indicates that there is sufficient power available to perform the memory operation. Resource(s) required to perform the memory operation that are already being used in the memory system are not counted against the variable credit value.
摘要翻译： 公开了用于电源管理的存储器系统和方法。 在一个实施例中，存储器系统保持指示当前可用于存储器系统中的存储器操作的功率量的可变信用值，可变信用值具有反映存储器系统的最大功率限制的上限。 存储器系统接收执行存储器操作的命令，其中需要多个资源来执行存储器操作，每个资源与信用值相关联。 在执行存储器操作之前，存储器系统检查可变信用值是否表明有足够的可用电力来执行存储器操作。 执行内存系统中已经使用的内存操作所需的资源不会计入可变的信用值。
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34.发明申请Reticle With Reduced Transmission Regions For Detecting A Defocus Condition In A Lithography Process 有权具有减少的传输区域的掩模版用于检测平版印刷工艺中的散焦条件公开(公告)号：US20160370598A1
公开(公告)日：2016-12-22
申请号：US14882258
申请日：2015-10-13
发明人： Akihiro Tobioka
CPC分类号： G02B27/32 , G02B5/0278 , G03F1/44 , G03F7/70641
摘要： A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is used to pattern a substrate has an asymmetric intensity. This allows the substrate to be patterned with an inspection mark which indicates whether a defocus condition exists, and whether there is a positive or negative defocus condition. Related methods use a reticle to form a pattern on a substrate and for adjusting a focus condition using a reticle.
摘要翻译： 用于半导体光刻工艺的掩模版包括具有降低的光透射系数的区域的玻璃板。 这些区域可以包括由激光脉冲形成的诸如裂纹或空隙的缺陷的元件阵列。 这些区域可以与掩模版底部的不透明材料中的开口相邻，以将开口与从顶部照射标线的光的一部分进行屏蔽。 结果，离开掩模版并用于图案化基板的光具有不对称的强度。 这允许基板被图案化，其具有指示是否存在散焦条件以及是否存在正或负散焦条件的检查标记。 相关方法使用掩模版在基板上形成图案并使用掩模版来调整聚焦条件。
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公开(公告)号：US20160351435A1
公开(公告)日：2016-12-01
申请号：US14723490
申请日：2015-05-28
发明人： Oshi Wakamatsu , Yasuhiro Domae
IPC分类号： H01L21/764 , H01L21/762 , H01L27/115
CPC分类号： H01L21/764 , H01L21/76224 , H01L27/11524
摘要： A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.
摘要翻译： 描述了在半导体衬底中形成浅沟槽隔离沟槽的方法。 该方法包括在衬底的区域中形成沟槽，在沟槽中形成第一介电材料，在第一介电材料之上形成第二电介质材料，在沟槽中的第一电介质材料中形成第一气隙， 在第一气隙上方的第二电介质材料中的第二气隙。
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公开(公告)号：US20160343449A1
公开(公告)日：2016-11-24
申请号：US14717582
申请日：2015-05-20
发明人： Aaron Lee , Zhenming Zhou , Mrinal Kochar , Cynthia Hua-Ling Hsu
CPC分类号： G11C16/3431 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C16/3445
摘要： A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.
摘要翻译： 具有存储器的存储设备可以包括用于开放块的读取干扰检测。 打开或部分编程的块可能会从读取开放块的编程部分而产生读取干扰错误。 任何读取干扰效应的检测对于开放块的继续编程可能是必需的，并且可以包括验证开放块的未编程部分中的字线是否处于擦除状态。 使用用于开放块的修改的擦除验证操作，其中编程的字线经受更高的擦除验证读取电压，而未编程的字线经受擦除验证偏置电压。
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37.发明申请LOW-POWER PARTIAL-PARALLEL CHIEN SEARCH ARCHITECTURE WITH POLYNOMIAL DEGREE REDUCTION 有权具有多项式减少功能的低功耗部分并行CHIEN搜索架构公开(公告)号：US20160329911A1
公开(公告)日：2016-11-10
申请号：US14706767
申请日：2015-05-07
发明人： XINMIAO ZHANG , ITAI DROR
IPC分类号： H03M13/15
CPC分类号： H03M13/1545 , G06F11/1076 , G06F11/108 , H03M13/1515 , H03M13/152 , H03M13/1525 , H03M13/157 , H03M13/617 , H03M13/6561
摘要： A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.
摘要翻译： 一种装置包括控制器，并且该控制器包括具有多组乘法器的根检测电路。 一种方法包括根据多项式的程度配置根检测电路。 响应于检测多项式的多个根的根，根据多项式程度降低（PDR）方案修改根检测电路的配置。 根据具体的实施方式，设备可以在数据存储设备，通信系统（例如，无线通信设备或有线通信设备）或其他电子设备中实现。
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38.发明授权Centralized variable rate serializer and deserializer for bad column management 有权集中可变速率序列化器和解串器，用于色谱柱管理不良公开(公告)号：US09490035B2
公开(公告)日：2016-11-08
申请号：US14104817
申请日：2013-12-12
发明人： Wanfang Tsai , YenLung Li , Chen Chen
CPC分类号： G11C29/82 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C29/808 , G11C2207/107
摘要： A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.
摘要翻译： 存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。 串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。 列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。 在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。 在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。
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公开(公告)号：US20160314843A1
公开(公告)日：2016-10-27
申请号：US14841182
申请日：2015-08-31
发明人： Huai-Yuan Tseng , Deepanshu Dutta
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C16/3468 , G11C2211/5621
摘要： Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between programming pulses, memory cells in the coarse phase are verified for a coarse phase verify level for a target data state and memory cells in the fine phase are verified for a fine phase verify level for the target data state, both in response to a single reference voltage applied on a common word line. For a memory cell in the coarse phase that has been verified to have reached the coarse phase verify level, the memory cell will be temporarily inhibited from programming for a next programming pulse and switched to the fine phase. For a memory cell in the fine phase that has been verified to have reached the fine phase verify level, the memory cell will be inhibited from further programming
摘要翻译： 编程非易失性存储器包括将一系列编程脉冲作为粗/精编程过程的一部分应用于存储器单元。 在编程脉冲之间，针对目标数据状态的粗略相位验证电平验证粗略相位中的存储器单元，并针对目标数据状态验证精细相位中的存储单元是否存在用于目标数据状态的精细相位验证电平，响应于单个 参考电压施加在公共字线上。 对于已经被验证已经达到粗略相位验证电平的粗略相位的存储单元，存储器单元将暂时禁止编程用于下一个编程脉冲并切换到精细相位。 对于已经验证已达到精细相位验证电平的精细相位的存储单元，存储器单元将被禁止进一步编程
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公开(公告)号：US20160313940A1
公开(公告)日：2016-10-27
申请号：US14692447
申请日：2015-04-21
发明人： Vikram Somaiya
CPC分类号： G06F3/0625 , G06F1/26 , G06F1/3268 , G06F1/3275 , G06F3/0685 , G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatuses for applying different voltages to an I/O interface (such as to the pads of the I/O interface) and determining the data integrity of communicating data (either transmitting to or receiving data from) to another device is disclosed. Data integrity may be measured in one of several ways, such as the window (or timing) at which data can be transmitted correctly using the different voltages. The determined data integrity may be compared with a minimum data integrity, such as a minimum window. In the event that the determined data integrity is greater or better than the minimum data integrity, then the voltage may be reduced and the data integrity determination may be performed again. In this way, the voltage applied to the I/O interface may be reduced while still meeting the minimum data integrity requirements.
摘要翻译： 公开了用于向I / O接口（例如到I / O接口的焊盘）施加不同电压并且确定向另一个设备传送数据或从其接收数据的数据完整性的方法和装置。 可以以几种方式之一来测量数据完整性，例如可以使用不同电压正确传输数据的窗口（或定时）。 所确定的数据完整性可以与诸如最小窗口的最小数据完整性进行比较。 在确定的数据完整性大于或优于最小数据完整性的情况下，可以减小电压并且可以再次执行数据完整性确定。 以这种方式，施加到I / O接口的电压可能会降低，同时仍然满足最低数据完整性要求。
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