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    Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
    31.
    发明授权
    Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit 有权
    用于从时钟数据恢复（CDR）单元捕获波形的表示的电路，装置和方法

    公开(公告)号：US07076377B2

    公开(公告)日：2006-07-11

    申请号：US10429514

    申请日：2003-05-05

    Applicant: Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

    Inventor： Dennis Kim ,  Jared Zerbe ,  Mark Horowitz ,  William Stonecypher

    IPC: G06F19/00

    CPC classification number: H03L7/0814 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/044 ,  H04L7/10

    Abstract: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second samplers to sample a data signal and output data and edge information in response to a data clock signal and an edge clock signal. A phase detector generates phase information in response to the data information and the edge information. A clock phase adjustment circuit generates the data clock signal and the edge clock signal in response to the data information during a synchronization mode. The clock phase adjustment circuit increments a phase of the data clock signal during a waveform capture mode.

    Abstract translation: 电路，装置和方法使用相移数据采样时钟在接收电路获得系统余量，同时允许CDR在实施例中与输入数据流保持同步。 在一个实施例中，电路包括第一和第二采样器，用于对数据信号进行采样，并响应于数据时钟信号和边沿时钟信号输出数据和边缘信息。 相位检测器响应于数据信息和边缘信息产生相位信息。 时钟相位调整电路在同步模式期间响应于数据信息产生数据时钟信号和边沿时钟信号。 时钟相位调整电路在波形捕获模式期间递增数据时钟信号的相位。

    Asynchronous request/synchronous data dynamic random access memory
    35.
    发明申请
    Asynchronous request/synchronous data dynamic random access memory 有权
    异步请求/同步数据动态随机存取存储器

    公开(公告)号：US20050243612A1

    公开(公告)日：2005-11-03

    申请号：US11153679

    申请日：2005-06-15

    Applicant: Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

    Inventor： Richard Barth ,  Mark Horowitz ,  Craig Hampel ,  Frederick Ware

    IPC: G06F12/00 ,  G06F13/16 ,  G11C5/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

    CPC classification number: G11C7/222 ,  G06F13/16 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

    Abstract: At page 54, please delete the current abstract and replace it with the following: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

    Abstract translation: 在第54页，请删除当前的摘要并将其替换为以下内容：集成电路存储器件包括使用第一控制信号加载地址的锁存电路。 第一控制信号的第一信号电平转换用于加载地址。 存储器阵列将数据存储在基于地址的存储器位置。 输出缓冲器在从第一信号电平转换起的一段时间后输出数据。 寄存器存储指定至少第一模式和第二模式之间的值。 当该值指定第一模式时，输出缓冲器响应于在第一信号电平转换之后发生的地址转换而输出该数据。 当该值指定第二模式时，输出缓冲器相对于外部时钟信号同步地输出数据。

    Technique for receiving differential multi-PAM signals
    37.
    发明申请
    Technique for receiving differential multi-PAM signals 有权
    接收差分多PAM信号的技术

    公开(公告)号：US20050069067A1

    公开(公告)日：2005-03-31

    申请号：US10673677

    申请日：2003-09-30

    Applicant: Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

    Inventor： Jared Zerbe ,  Grace Tsang ,  Mark Horowitz ,  Bruno Garlepp ,  Carl Werner

    IPC: H04L25/49 ,  H04L27/06

    CPC classification number: H04L25/4917

    Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.

    Abstract translation: 公开了一种用于接收差分多PAM信号的技术。 在一个特定的示例性实施例中，该技术可以被实现为差分多PAM提取器电路。 在该特定示例性实施例中，差分多PAM提取器电路包括被配置为接收差分多PAM输入信号和第一差分参考信号的高LSB采样器电路，并且产生第一差分采样输出信号。 差分多PAM提取器电路还包括被配置为接收差分多PAM输入信号和第二差分参考信号的低LSB采样器电路，并且产生第二差分采样输出信号。 差分多PAM提取器电路还包括组合器电路，其被配置为接收第一差分采样输出信号和第二差分采样输出信号，并且产生指示差分多PAM输入信号的LSB值的差分LSB输出信号。

    Integrated circuit I/O using a high performance bus interface
    39.
    发明授权
    Integrated circuit I/O using a high performance bus interface 失效
    集成电路I / O采用高性能总线接口

    公开(公告)号：US06598171B1

    公开(公告)日：2003-07-22

    申请号：US08829459

    申请日：1997-03-28

    Applicant: Michael Farmwald ,  Mark Horowitz

    Inventor： Michael Farmwald ,  Mark Horowitz

    IPC: G11C804

    CPC classification number: G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G06F13/4239 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

    Abstract translation: 本发明包括一个包括至少两个半导体器件的存储器子系统，包括连接到总线的至少一个存储器件，其中总线包括用于承载所有存储器件所需的所有地址，数据和控制信息的多条总线 ，其中控制信息包括设备选择信息，并且总线具有比单个地址中的位数少得多的总线，并且总线承载设备选择信息，而不需要直接连接到各个设备的单独的设备选择线 本发明还包括用于主设备和从设备在总线上进行通信和每个设备中的寄存器的协议，以区分每个设备，并允许总线请求被引导到单个或所有设备。 本发明包括对现有技术设备的修改，以允许它们实现本发明的新特征。 在一个优选实施方式中，8个总线数据线和一个AddressValid总线携带地址，数据和控制信息，用于高达40位宽的存储器地址。

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