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    Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture
    32.
    发明公开
    Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture 审中-公开

    公开(公告)号：US20240311334A1

    公开(公告)日：2024-09-19

    申请号：US18624877

    申请日：2024-04-02

    Applicant: Rambus Inc.

    Inventor： Steven C. Woo ,  Michael Raymond Miller

    IPC: G06F15/80

    CPC classification number: G06F15/8061

    Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

    Hybrid memory module
    36.
    发明授权
    Hybrid memory module 有权

    公开(公告)号：US12072802B2

    公开(公告)日：2024-08-27

    申请号：US18152642

    申请日：2023-01-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G06F12/00 ,  G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/7203

    Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

    Buffer circuit with data bit inversion
    38.
    发明授权
    Buffer circuit with data bit inversion 有权

    公开(公告)号：US12067285B2

    公开(公告)日：2024-08-20

    申请号：US18093258

    申请日：2023-01-04

    Applicant: Rambus Inc.

    Inventor： Scott C. Best

    IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

    CPC classification number: G06F3/0656 ,  G06F3/0626 ,  G06F3/0673 ,  G11C7/1006 ,  G11C5/04

    Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

    UNSUCCESSFUL WRITE RETRY BUFFER
    40.
    发明公开
    UNSUCCESSFUL WRITE RETRY BUFFER 审中-公开

    公开(公告)号：US20240273038A1

    公开(公告)日：2024-08-15

    申请号：US18586867

    申请日：2024-02-26

    Applicant: Rambus Inc.

    Inventor： Hongzhong ZHENG ,  Brent Haukness

    IPC: G06F13/16 ,  G06F5/14

    CPC classification number: G06F13/1626 ,  G06F5/14

    Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

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