公开(公告)号：US20050018488A1

公开(公告)日：2005-01-27

申请号：US10888944

申请日：2004-07-08

Applicant: Dong-Hwan Kim ,  Yeong-Taek Lee

Inventor： Dong-Hwan Kim ,  Yeong-Taek Lee

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/30 ,  G11C11/34

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5642

Abstract: There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

Abstract translation: 提供了一种具有多电平单元的闪存器件及其读取和编程方法。 具有多电平单元的闪速存储器件包括存储单元阵列，用于对位线进行预充电的单元，用于向位线提供电压的位线电压供应电路，以及每一个执行与位线不同的功能的第一至第三锁存电路 彼此。 读取和编程方法由LSB和MSB读取和编程操作执行。 通过读取LSB两次并通过读取MSB一次来实现存储器件中的读取方法。 通过编程LSB一次并编程MSB一次来实现编程方法。 具有多级数据的数据可以通过两次编程操作被编程到存储器单元中。

公开(公告)号：US20050006692A1

公开(公告)日：2005-01-13

申请号：US10840580

申请日：2004-05-07

Applicant: Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

Inventor： Moo-Sung Kim ,  Yeong-Taek Lee ,  Seung-Jae Lee

IPC: G11C16/06 ,  G11C8/00 ,  G11C11/56 ,  G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  H01L27/115

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  H01L27/115

Abstract: A flash memory device may include a memory cell array having a plurality of word lines, bit lines, and memory cells. Each memory cell may be arranged at an intersection of a corresponding word line and a corresponding bit line. The device may include a bit line voltage setting circuit for setting a voltage on a bit line of a given memory cell to be programmed to a variable bit line voltage or to a ground voltage. A variable bit line voltage generating circuit may be provided in the flash memory device for generating the variable bit line voltage. To facilitating programming of the device, a bit line voltage of a given memory cell to be programmed may be set based on a supply voltage of the device, so as to maintain a voltage difference based on the set bit line voltage above a given threshold voltage.

Abstract translation: 闪存器件可以包括具有多个字线，位线和存储器单元的存储单元阵列。 每个存储单元可以被布置在对应的字线和对应的位线的交叉点处。 该设备可以包括位线电压设置电路，用于将要编程的给定存储器单元的位线上的电压设置为可变位线电压或接地电压。 可变位线电压产生电路可以设置在闪存器件中，用于产生可变位线电压。 为了便于设备的编程，可以基于设备的电源电压来设置要编程的给定存储器单元的位线电压，以便基于设定的位线电压维持高于给定阈值电压的电压差 。

公开(公告)号：US06469933B2

公开(公告)日：2002-10-22

申请号：US09952628

申请日：2001-09-13

Applicant: Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

Inventor： Sun-Mi Choi ,  Yeong-Taek Lee ,  Young-Ho Lim

IPC: G11C1604

CPC classification number: G11C16/3427 ,  G11C16/10 ,  G11C16/12

Abstract: Disclosed is a method for programming a non-volatile semiconductor memory device that avoids the program disturb problem. In the programming method, ground voltage is applied to a first bit line corresponding to a memory cell to be programmed, and power supply voltage is applied to a second bit line corresponding to a memory cell to be prevented from being programmed. Next, a program voltage is applied to a word line connected to the memory cell to be programmed. The program voltage is stepped up to a desired voltage level of each program cycle from the first voltage thereby to reduce coupling between selected and non-selected bit and word lines.

Abstract translation: 公开了一种用于编程避免程序干扰问题的非易失性半导体存储器件的方法。 在编程方法中，将接地电压施加到与待编程的存储单元相对应的第一位线，并且将电源电压施加到对应于存储器单元的第二位线以防止被编程。 接下来，将编程电压施加到连接到要编程的存储器单元的字线。 编程电压从第一电压升高到每个编程周期的期望电压电平，从而减少选定位和未选择位和字线之间的耦合。

公开(公告)号：US09418739B2

公开(公告)日：2016-08-16

申请号：US14616806

申请日：2015-02-09

Applicant: Yong-Kyu Lee ,  Yeong-Taek Lee

Inventor： Yong-Kyu Lee ,  Yeong-Taek Lee

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72

Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

Abstract translation: 操作存储设备的方法包括： 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压，向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压，以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压，并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

公开(公告)号：US20160027485A1

公开(公告)日：2016-01-28

申请号：US14683186

申请日：2015-04-10

Applicant: HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON ,  CHI-WEON YOON

Inventor： HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  DAE-SEOK BYEON ,  CHI-WEON YOON

IPC: G11C7/22 ,  G06F11/07 ,  G11C7/12

CPC classification number: G11C7/22 ,  G06F11/073 ,  G06F11/076 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/004 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2213/72

Abstract: A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.

Abstract translation: 一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

公开(公告)号：US20150287460A1

公开(公告)日：2015-10-08

申请号：US14616806

申请日：2015-02-09

Applicant: YONG-KYU LEE ,  YEONG-TAEK LEE

Inventor： YONG-KYU LEE ,  YEONG-TAEK LEE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/72

Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

Abstract translation: 操作存储器件的方法包括： 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压，向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压，以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压，并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

公开(公告)号：US20140160831A1

公开(公告)日：2014-06-12

申请号：US14100183

申请日：2013-12-09

Applicant: Sung-Yeon Lee ,  Yeong-Taek Lee ,  Bo-Geun Kim

Inventor： Sung-Yeon Lee ,  Yeong-Taek Lee ,  Bo-Geun Kim

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C7/00 ,  G11C7/1096 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

Abstract: Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result. Related nonvolatile memory devices are also provided.

Abstract translation: 提供了非易失性存储器件的驱动方法。 该驱动方法包括：将基于先前写入操作调整的起始脉冲提供给电阻式存储单元以写入数据，使用起始脉冲验证数据是否被准确写入，并且通过增量执行对电阻式存储器单元的写入操作 根据验证结果，单向写入方法或递减单向写入方法。 还提供了相关的非易失性存储器件。

公开(公告)号：US08315105B2

公开(公告)日：2012-11-20

申请号：US13153285

申请日：2011-06-03

Applicant: Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Doo-Gon Kim ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/14

Abstract: An erasing method of post-programming in a nonvolatile memory device. The method includes post-programming dummy memory cells; verifying whether threshold voltages of the dummy memory cells are greater than or equal to a first voltage; post-programming normal memory cells; and verifying whether threshold voltages of the normal memory cells are greater than or equal to a second voltage. The first voltage is different from the second voltage.

Abstract translation: 一种在非易失性存储器件中进行后编程的擦除方法。 该方法包括后编程虚拟存储器单元; 验证所述伪存储单元的阈值电压是否大于或等于第一电压; 后编程正常记忆单元; 以及验证所述正常存储单元的阈值电压是否大于或等于第二电压。 第一电压与第二电压不同。

公开(公告)号：US08279664B2

公开(公告)日：2012-10-02

申请号：US12879157

申请日：2010-09-10

Applicant: Sang-Hoan Chang ,  Seong-Moo Heo ,  Kwang-Suk Yu ,  Yeong-Taek Lee ,  Woo-Yeong Cho

Inventor： Sang-Hoan Chang ,  Seong-Moo Heo ,  Kwang-Suk Yu ,  Yeong-Taek Lee ,  Woo-Yeong Cho

IPC: G11C11/00

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2013/0092 ,  G11C2213/56

Abstract: In a method of programming a phase change memory device, write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying verification pulses to each of the phase-change memory cells. A number of applications for the verification pulses and the intervals between respective applications of the verification pulses are varied in accordance with a verification result for each of the phase-change memory cells.

Abstract translation: 在对相变存储器件进行编程的方法中，通过向多个相变存储器单元中的每一个施加写脉冲，将写数据编程在多个相变存储器单元中。 通过将验证脉冲应用于每个相变存储单元来验证每个相变存储单元是否被编程。 用于验证脉冲的多个应用以及验证脉冲的相应应用之间的间隔根据每个相变存储单元的验证结果而变化。

公开(公告)号：US20120140557A1

公开(公告)日：2012-06-07

申请号：US13372525

申请日：2012-02-14

Applicant: Ki-tae PARK ,  Yeong-taek LEE

Inventor： Ki-tae PARK ,  Yeong-taek LEE

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C16/3418

Abstract: Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

Abstract translation: 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。