公开(公告)号：US5544125A

公开(公告)日：1996-08-06

申请号：US383866

申请日：1995-02-06

申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种改进的读/写布置，用于这样的半导体存储器电路，其包括在写入操作期间防止公共读取线与数据线连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

公开(公告)号：US5502820A

公开(公告)日：1996-03-26

申请号：US385656

申请日：1995-02-08

申请人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

发明人： Atsushi Hiraishi ,  Takashi Akioka ,  Yutaka Kobayashi ,  Yuji Yokoyama ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Hideaki Uchida ,  Akira Ide

IPC分类号： G11C11/417 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/088 ,  H03K19/0944 ,  G06F13/00

CPC分类号： H03K19/09448 ,  H03K17/164 ,  H03K19/00361

摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

摘要翻译： 提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。 缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。 这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。 例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。 电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

公开(公告)号：US5304868A

公开(公告)日：1994-04-19

申请号：US783781

申请日：1991-10-29

申请人： Yuji Yokoyama ,  Kazuyuki Miyazawa ,  Hitoshi Miwa ,  Shoji Wada

发明人： Yuji Yokoyama ,  Kazuyuki Miyazawa ,  Hitoshi Miwa ,  Shoji Wada

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C8/06 ,  G11C11/417 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/02 ,  G11C8/00

CPC分类号： H03K19/0136 ,  G11C7/1051 ,  G11C8/06 ,  H03K19/09448

摘要： A non-inverting buffer circuit device suited for an input buffer circuit of a semiconductor memory is provided so that the number of logic gate stages can be reduced to realize a high speed operation. The circuit is designed in such a way that an MOS transistor at an input stage drives a bipolar transistor at an output stage to produce an output. An n-channel MOS transistor and a p-channel MOS transistor connected in parallel between the base and the collector of the bipolar transistor are on/off controlled by an inverted signal of the input digital signal and a non-inverted signal thereof, respectively. In another aspect, the input buffer circuit includes an inverted signal outputting circuit, and a non-inverted signal outputting circuit in the set mode the input signal in the non-inverted state and outputting in the reset mode the signal at the prescribed potential. The inverted signal outputting circuit includes a bipolar transistor producing an output signal at its collector potential, a first switching circuit for controlling supply of a collector current to the bipolar transistor, an n-channel MOS transistor, connected in parallel between the base and the collector of the bipolar transistor, for supplying a base current to the bipolar transistor in accordance with the input signal, and a second switching circuit for controlling supply of the base current to the bipolar transistor, wherein the first switching circuit and the second switching circuit are selectively on-off controlled.

摘要翻译： 提供了适用于半导体存储器的输入缓冲电路的非反相缓冲电路装置，可以减少逻辑门级的数量，实现高速运算。 该电路被设计成使得输入级的MOS晶体管在输出级驱动双极晶体管以产生输出。 并联连接在双极型晶体管的基极和集电极之间的n沟道MOS晶体管和p沟道MOS晶体管分别通过输入数字信号的反相信号和非反相信号进行开/关控制。 在另一方面，输入缓冲电路包括反相信号输出电路和非反相信号输出电路，在设定模式下输入处于非反相状态的输入信号，并以复位模式输出处于规定电位的信号。 反相信号输出电路包括产生其集电极电位的输出信号的双极晶体管，用于控制向双极晶体管供给集电极电流的第一开关电路，并联在基极和集电极之间的n沟道MOS晶体管 用于根据输入信号向双极晶体管提供基极电流;以及第二开关电路，用于控制对双极晶体管的基极电流的供应，其中第一开关电路和第二开关电路选择性地 开关控制。

公开(公告)号：US09559383B2

公开(公告)日：2017-01-31

申请号：US14372299

申请日：2012-01-17

申请人： Masahiro Morita ,  Toshihiko Mitsuhashi ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto ,  Tatsuya Hashimoto

发明人： Masahiro Morita ,  Toshihiko Mitsuhashi ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto ,  Tatsuya Hashimoto

IPC分类号： H01M10/05 ,  H01M10/0567 ,  H01M10/0525 ,  H01M10/42 ,  H01M2/34

CPC分类号： H01M10/0567 ,  H01M2/345 ,  H01M10/0525 ,  H01M10/4235 ,  H01M2220/20 ,  Y02E60/122 ,  Y02T10/7011

摘要： The present invention provides a sealed lithium secondary battery in which redox shuttle reactions of an aromatic compound that is an overcharge inhibitor are inhibited, and the aromatic compound decomposes appropriately, and a desired amount of gas can be generated more stably than in conventional instances, even in high-temperature environments. In the sealed lithium secondary battery (100), an electrode assembly (80) and an electrolyte are accommodated in a battery case (50) that is provided with a current interrupt device (30). The electrolyte comprises a compound that is capable of suppressing drops in viscosity of the electrolyte as a result of a rise in temperature in a temperature region up to 100° C., and an aromatic compound capable of generating hydrogen gas when a predetermined battery voltage is exceeded.

摘要翻译： 本发明提供一种密封的锂二次电池，其中抑制了作为过充电抑制剂的芳族化合物的氧化还原穿梭反应，并且芳族化合物适当地分解，并且与常规情况相比可以更稳定地产生所需量的气体，甚至 在高温环境中。 在密封锂二次电池（100）中，电极组件（80）和电解质容纳在设置有电流中断装置（30）的电池壳体（50）中。 该电解质包含能够抑制由于温度上升到100℃而导致的电解液粘度降低的化合物，以及当预定的电池电压为 超过了

公开(公告)号：US20140342200A1

公开(公告)日：2014-11-20

申请号：US14372299

申请日：2012-01-17

申请人： Masahiro Morita ,  Toshihiko Mitsuhashi ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto ,  Tatsuya Hashimoto

发明人： Masahiro Morita ,  Toshihiko Mitsuhashi ,  Keisuke Ohara ,  Yuji Yokoyama ,  Yusuke Fukumoto ,  Tatsuya Hashimoto

IPC分类号： H01M10/0567 ,  H01M10/42 ,  H01M10/0525

CPC分类号： H01M10/0567 ,  H01M2/345 ,  H01M10/0525 ,  H01M10/4235 ,  H01M2220/20 ,  Y02E60/122 ,  Y02T10/7011

摘要： The present invention provides a sealed lithium secondary battery in which redox shuttle reactions of an aromatic compound that is an overcharge inhibitor are inhibited, and the aromatic compound decomposes appropriately, and a desired amount of gas can be generated more stably than in conventional instances, even in high-temperature environments. In the sealed lithium secondary battery (100), an electrode assembly (80) and an electrolyte are accommodated in a battery case (50) that is provided with a current interrupt device (30). The electrolyte comprises a compound that is capable of suppressing drops in viscosity of the electrolyte as a result of a rise in temperature in a temperature region up to 100° C., and an aromatic compound capable of generating hydrogen gas when a predetermined battery voltage is exceeded.

摘要翻译： 本发明提供一种密封的锂二次电池，其中抑制了作为过充电抑制剂的芳族化合物的氧化还原穿梭反应，并且芳族化合物适当地分解，并且与常规情况相比可以更稳定地产生所需量的气体，甚至 在高温环境中。 在密封的锂二次电池（100）中，电极组件（80）和电解质容纳在设置有电流中断装置（30）的电池壳体（50）中。 该电解质包含能够抑制由于温度上升到100℃而导致的电解液粘度降低的化合物，以及当预定的电池电压为 超过了

公开(公告)号：US20090256599A1

公开(公告)日：2009-10-15

申请号：US12420253

申请日：2009-04-08

申请人： Toshio SHINOMIYA ,  Akio KOYAMA ,  Yuji YOKOYAMA

发明人： Toshio SHINOMIYA ,  Akio KOYAMA ,  Yuji YOKOYAMA

IPC分类号： H03L7/00

CPC分类号： H03K17/223 ,  G06F1/24

摘要： In a semiconductor integrated circuit device generating internal power from external power, an abnormal operation may occur due to an indefinite state of a control signal when the external power is applied and the internal power rises. The semiconductor integrated circuit includes an internal power generating circuit, a control circuit receiving internal power and supplying a first control signal, and a power-on reset circuit generating a reset signal at rising of the internal power. When internal power rises, the reset signal masks an indefinite state of the first control signal supplied from the control circuit.

摘要翻译： 在从外部电力产生内部电力的半导体集成电路装置中，当施加外部电力并且内部电力上升时，可能由于控制信号的不确定状态而发生异常操作。 半导体集成电路包括内部发电电路，接收内部电力并提供第一控制信号的控制电路，以及在内部电力上升时产生复位信号的上电复位电路。 当内部电源上升时，复位信号屏蔽从控制电路提供的第一控制信号的不确定状态。

公开(公告)号：US07113434B2

公开(公告)日：2006-09-26

申请号：US10823664

申请日：2004-04-14

申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

公开(公告)号：US06962863B2

公开(公告)日：2005-11-08

申请号：US10704684

申请日：2003-11-12

申请人： Yuji Yokoyama

发明人： Yuji Yokoyama

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/31 ,  H01L23/522 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L23/3192 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22 and which includes a larger layer number of insulation films 24, 26 28 covering the side wall of the interconnection layer 14 at the side wall of the cap insulation film 22 than a layer number of insulation films 24, 26 at the side wall of the cap insulation film 22. Accordingly, the sidewall insulation film can be thickened at the side wall of the interconnection layer 14, whereby a parasitic capacitance between the interconnection layer 14 and the electrodes 32 adjacent to the interconnection layer 14 through the sidewall insulation film can be low.

摘要翻译： 半导体器件包括形成在衬底10上的互连层14，形成在互连层14的上表面上的帽绝缘膜22和形成在互连层14的侧壁上的侧壁绝缘膜 绝缘膜22，其包括覆盖在绝缘膜22的侧壁处的互连层14的侧壁的绝缘膜24,26,28的层数比在侧壁处的绝缘膜24,26的层数更大 盖绝缘膜22。 因此，可以在互连层14的侧壁处增厚侧壁绝缘膜，由此通过侧壁绝缘膜在互连层14和与互连层14相邻的电极32之间的寄生电容可以较低。

公开(公告)号：US06714477B2

公开(公告)日：2004-03-30

申请号：US10187947

申请日：2002-07-03

申请人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

发明人： Michiaki Nakayama ,  Hideki Sakakibara ,  Toru Kobayashi ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Hideo Sawamoto ,  Masaji Kume

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4093

摘要： Read buffers (RB0-RB3) are capable of holding data read out from a plurality of memory blocks (BNK0-BNK7) that are capable of parallel operation in response to a state in which the read data cannot be externally outputted from an external interface means; and, selection means (40, 41, 42) are provided for selecting data read out from one of the memory blocks, or data read out from one of the read buffers, and for feeding it to the external interface means, while the external-output-incapable state is not present. In this way, when there is a possibility that an output of read data will cause a resource competition, this read data is stored in a read buffer, and when there is no such possibility, then the read data can be externally outputted directly, thereby improving the throughput of read data output operations.

摘要翻译： 读取缓冲器（RB0-RB3）能够保持从能够并行操作的多个存储器块（BNK0-BNK7）中读出的数据，以响应于从外部接口装置不能从外部输出读取的数据的状态 ; 并且提供选择装置（40,41,42），用于选择从一个存储块读出的数据，或从读取缓冲器之一读出的数据，并将其馈送到外部接口装置， 输出无能力状态不存在。 这样，当读取数据的输出有可能导致资源竞争时，该读取数据被存储在读取缓冲器中，并且当不存在这种可能性时，可以直接从外部输出读取的数据，由此 提高读取数据输出操作的吞吐量。

公开(公告)号：US06570800B2

公开(公告)日：2003-05-27

申请号：US09756800

申请日：2001-01-10

申请人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

发明人： Yousuke Tanaka ,  Masahiro Katayama ,  Yuji Yokoyama ,  Hiroshi Akasaki ,  Shuichi Miyaoka ,  Toru Kobayashi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4096

摘要： The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

摘要翻译： 以时钟信号周期多次的周期改变的列地址选通信号（CAS）被输入到存储块（MBK0〜MBKn）。 当列地址信号（CASADR）为“0”时，每个周期输出从存储单元阵列（10）读出并与并行/串行转换器电路（21）并行/串行转换的多个串行数据， 改变了 并行数据输入到存储器块，并且与时钟信号周期同步地由串行/并行转换器电路（25）串行/并行转换的并行数据被写入存储单元阵列中。 以这种方式，列地址选通信号的访问规范每时钟信号的n个周期改变一次，从而允许更快速的存储器操作。