公开(公告)号：US09922608B2

公开(公告)日：2018-03-20

申请号：US14722620

申请日：2015-05-27

Applicant: Apple Inc.

Inventor： Chaohao Wang ,  Brijesh Tripathi ,  Christopher Philip Alan Tann ,  David S. Zalatimo ,  Guy Cote ,  Hao Nan ,  Marc Albrecht ,  Paolo Sacchetto ,  Sandro H. Pintz

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G2320/0204 ,  G09G2320/0247 ,  G09G2320/0257 ,  G09G2320/046 ,  G09G2340/0435 ,  G09G2360/16

Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.

公开(公告)号：US20170092236A1

公开(公告)日：2017-03-30

申请号：US14869148

申请日：2015-09-29

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Arthur L. Spence ,  Joshua P. de Cesare ,  Ilie Garbacea ,  Guy Cote ,  Mahesh B. Chappalli ,  Malcolm D. Gray

IPC: G09G5/395

CPC classification number: G09G5/395 ,  G06F3/1407 ,  G06F3/147 ,  G09G2310/08 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2360/127

Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

公开(公告)号：US20170092210A1

公开(公告)日：2017-03-30

申请号：US14866539

申请日：2015-09-25

Applicant: Apple Inc.

Inventor： Christopher P. Tann ,  Chaohao Wang ,  David S. Zalatimo ,  Guy Cote ,  Brijesh Tripathi

IPC: G09G3/36

CPC classification number: G09G3/3614 ,  G09G3/20 ,  G09G2310/0256 ,  G09G2310/08 ,  G09G2320/0204 ,  G09G2330/021 ,  G09G2340/0435

Abstract: Devices and methods for reducing and/or substantially eliminating pixel charge imbalance due to variable refresh rates are provided. By way of example, a method includes providing a first frame of image data via a processor to a plurality of pixels of the display during a first frame period corresponding to a first refresh rate, and providing a second frame of image data to the plurality of pixels of the display during a second frame period corresponding to a second refresh rate. The method further includes dividing the first frame period into a first frame sub-period and a second frame sub-period, and driving the plurality of pixels of the display with the first frame of image data during the first frame sub-period and the second frame sub-period.

公开(公告)号：US20160293137A1

公开(公告)日：2016-10-06

申请号：US14676544

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Peter F. Holland ,  Guy Cote

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G5/363 ,  G09G5/391 ,  G09G2340/0428 ,  G09G2360/02

Abstract: Systems, apparatuses, and methods for passing source pixel data through a display control unit. A display control unit includes N-bit pixel component processing lanes for processing source pixel data. When the display control unit receives M-bit source pixel components, wherein ‘M’ is greater than ‘N’, the display control unit may assign the M-bit source pixel components to the N-bit processing lanes. Then, the M-bit source pixel components may passthrough the pixel component processing elements of the display control unit without being modified.

Abstract translation: 用于通过显示控制单元传送源像素数据的系统，装置和方法。 显示控制单元包括用于处理源像素数据的N位像素分量处理通道。 当显示控制单元接收M位大于'N'的M位源像素分量时，显示控制单元可以将M位源像素分量分配给N位处理通道。 然后，M位源像素分量可以直接通过显示控制单元的像素分量处理元件而不被修改。

公开(公告)号：US20160292094A1

公开(公告)日：2016-10-06

申请号：US14676174

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许在通信链路上执行周期性校准操作。 控制器可以基于初始值来确定与通信链路一起使用的参考电压的多个可能值。 可以使用每个可能的值执行校准操作，并且基于在校准操作期间测量的数据眼睛的宽度来评估操作的结果。 然后，控制器可以根据多个可能值中的每一个的分数从多个可能值中选择参考电压的新值。

公开(公告)号：US20160291625A1

公开(公告)日：2016-10-06

申请号：US14673326

申请日：2015-03-30

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Eric G. Smith ,  Erik P. Machnicki ,  Jung Wook Cho ,  Khaled M. Alashmouny ,  Kiran B. Kattel ,  Vijay M. Bettada ,  Bo Yang ,  Wenlong Wei

IPC: G05F3/02

CPC classification number: G05F3/02 ,  G06F1/324 ,  G06F1/3296

Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Abstract translation: 公开了一种欠压检测电路及其运算方法。 在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。 逻辑电路被耦合以从第一和第二比较器接收信号。 在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。 提供给功能电路的时钟信号可以响应于指示而被节流。 如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

公开(公告)号：US20160274690A1

公开(公告)日：2016-09-22

申请号：US15167775

申请日：2016-05-27

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Jean-Pierre S. Guillou

IPC: G06F3/041 ,  G06T19/00 ,  G09G3/20

CPC classification number: G06F3/041 ,  G06T19/006 ,  G09G3/20 ,  G09G2320/029 ,  G09G2320/0606 ,  G09G2320/0613 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2354/00 ,  G09G2360/18

Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.

公开(公告)号：US09286855B2

公开(公告)日：2016-03-15

申请号：US14683240

申请日：2015-04-10

Applicant: Apple Inc.

Inventor： Brijesh Tripathi

IPC: H04N21/43 ,  H04J3/06 ,  G09G5/00 ,  G06T1/20 ,  G09G3/20 ,  G09G5/12 ,  G09G5/36

CPC classification number: G09G5/008 ,  G06T1/20 ,  G06T2200/28 ,  G09G3/2096 ,  G09G5/003 ,  G09G5/006 ,  G09G5/12 ,  G09G5/363 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2360/18 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/12 ,  H04J3/0667 ,  H04N21/4302 ,  H04N21/4305

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The sink processor may be operable to send a synchronization signal to the source processor through the interface. The source processor may be operable, dependent upon the synchronization signal, to send data to the sink processor.

公开(公告)号：US20150362947A1

公开(公告)日：2015-12-17

申请号：US14833424

申请日：2015-08-24

Applicant: Apple Inc.

Inventor： Brijesh Tripathi

IPC: G06F1/12 ,  G09G5/12 ,  G09G5/00

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/047 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路，辅助链路和热插拔检测链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令。 源处理器可以经由主链路将初始化参数发送到宿处理器。 初始化参数可以包括时钟数据恢复锁定参数和空闲参数。 在初始化参数之后，源处理器可以经由主链路向宿处理器发送同步信号。 然后，源处理器可以经由主链路向宿处理器发送睡眠命令。

公开(公告)号：US20150347287A1

公开(公告)日：2015-12-03

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. De Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。