公开(公告)号：US20240038833A1

公开(公告)日：2024-02-01

申请号：US18222086

申请日：2023-07-14

Applicant: Applied Materials, Inc.

Inventor： Fredrick Fishburn ,  Tomohiko Kitajima ,  Qian Fu ,  Srinivas Guggilla ,  Hang Yu ,  Jun Feng ,  Shih Chung Chen ,  Lakmal C. Kalutarage ,  Jayden Potter ,  Karthik Janakiraman ,  Deenesh Padhi ,  Yifeng Zhou ,  Yufeng Jiang ,  Sung-Kwan Kang

IPC: H10B12/00

CPC classification number: H01L28/91 ,  H01L28/92 ,  H10B12/03 ,  H10B12/30

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where carbon is used as the removable mold material for the formation of a DRAM capacitor. A dense, high-temperature (500° C. or greater) PECVD carbon material is used as the removable mold material, e.g., the core material, instead of oxide. The carbon material can be removed by isotropic etching with exposure to radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

公开(公告)号：US20230420232A1

公开(公告)日：2023-12-28

申请号：US18243436

申请日：2023-09-07

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Ning Li ,  Chang Seok Kang ,  Naomi Yoshida

IPC: H01J37/32 ,  C23C16/34 ,  C23C16/38 ,  H01L21/67 ,  C23C16/36 ,  H01L21/02 ,  C23C16/02 ,  C23C16/56

CPC classification number: H01J37/32899 ,  C23C16/342 ,  C23C16/38 ,  C23C16/345 ,  H01L21/67167 ,  C23C16/36 ,  H01L21/0234 ,  C23C16/0227 ,  C23C16/56 ,  H01L21/0217 ,  H01J2237/20278 ,  H01J2237/336 ,  H01J2237/335 ,  H01J37/32816 ,  H01J2237/332

Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

公开(公告)号：US20230371246A1

公开(公告)日：2023-11-16

申请号：US18141570

申请日：2023-05-01

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Gill Yong Lee

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/02

Abstract: Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.

公开(公告)号：US20230164993A1

公开(公告)日：2023-05-25

申请号：US18055058

申请日：2022-11-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Balasubramanian Pranatharthiharan ,  Mukund Srinivasan

IPC: H01L27/11578 ,  G11C5/06 ,  H01L27/1157

CPC classification number: H01L27/11578 ,  G11C5/063 ,  H01L27/1157

Abstract: Described is a memory device including a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate. Each of the plurality of memory cells comprises a discrete blocking oxide layer, a charge trap layer, and a tunnel oxide layer. The blocking oxide layer is discrete between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trap layer is discrete between each of the plurality of memory cells. The charge trap layer has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness.

公开(公告)号：US20230146831A1

公开(公告)日：2023-05-11

申请号：US17902838

申请日：2022-09-04

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Gill Yong Lee ,  Fred Fishburn ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Sony Varghese

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

公开(公告)号：US11545504B2

公开(公告)日：2023-01-03

申请号：US17228034

申请日：2021-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US10886140B2

公开(公告)日：2021-01-05

申请号：US16523262

申请日：2019-07-26

Applicant: Applied Materials, Inc.

Inventor： Shishi Jiang ,  Pramit Manna ,  Bo Qi ,  Abhijit Basu Mallick ,  Rui Cheng ,  Tomohiko Kitajima ,  Harry S. Whitesell ,  Huiyuan Wang

IPC: H01L21/311 ,  H01L21/02 ,  H01L27/11551 ,  H01L27/11578

Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

公开(公告)号：US20200035505A1

公开(公告)日：2020-01-30

申请号：US16523262

申请日：2019-07-26

Applicant: Applied Materials, Inc.

Inventor： Shishi Jiang ,  Pramit Manna ,  Bo Qi ,  Abhijit Basu Mallick ,  Rui Cheng ,  Tomohiko Kitajima ,  Harry S. Whitesell ,  Huiyuan Wang

IPC: H01L21/311 ,  H01L21/02

Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

公开(公告)号：US20160284615A1

公开(公告)日：2016-09-29

申请号：US15173584

申请日：2016-06-03

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Jeffrey Drue David ,  Jun Qian ,  Taketo Sekine ,  Garlen C. Leung ,  Sidney P. Huey

IPC: H01L21/66 ,  H01L21/321 ,  B24B49/10 ,  H01L21/311 ,  B24B37/013 ,  H01L21/3105 ,  H01L21/67

CPC classification number: H01L22/26 ,  B24B37/013 ,  B24B49/105 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/67075 ,  H01L21/67092 ,  H01L21/67253 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being a measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of an outer layer over the at least one layer, after deposition of the outer layer over the at least one layer and during polishing of the outer layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract translation: 控制抛光的方法包括存储基底测量，所述基底测量是沉积覆盖在半导体晶片上的至少一个层之后并且在外层沉积外层之后在所述至少一个层上沉积之后的衬底的测量值 层，并且在衬底上的外层的抛光期间，从原位监测系统接收衬底的原始测量序列，对原始测量序列中的每个原始测量进行归一化，以生成标准化的序列 使用原始测量和基础测量的测量，以及至少基于归一化测量的顺序来确定抛光终点或抛光速率的调整中的至少一个。

公开(公告)号：US20250037989A1

公开(公告)日：2025-01-30

申请号：US18907769

申请日：2024-10-07

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Shuaidi Zhang ,  Mihaela A. Balseanu ,  Qi Gao ,  Rajesh Prasad ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Deven Matthew Raj Mittal ,  Kyu-Ha Shim

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.