公开(公告)号：US20160260684A1

公开(公告)日：2016-09-08

申请号：US14638925

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Kwan-Yu Lai ,  Mengzhi Pang ,  Chonghua Zhong ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。

公开(公告)号：US11967528B2

公开(公告)日：2024-04-23

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20240105702A1

公开(公告)日：2024-03-28

申请号：US18178820

申请日：2023-03-06

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/36 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13082 ,  H01L2224/32245 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

公开(公告)号：US20230154897A1

公开(公告)日：2023-05-18

申请号：US18156287

申请日：2023-01-18

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/24 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/24 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US20230017445A1

公开(公告)日：2023-01-19

申请号：US17815893

申请日：2022-07-28

Applicant: Apple Inc.

Inventor： Kunzhong Hu ,  Chonghua Zhong ,  Jiongxin Lu ,  Jun Zhai

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L23/488

Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

公开(公告)号：US11069665B2

公开(公告)日：2021-07-20

申请号：US16205679

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Jun Zhai ,  Long Huang ,  Mengzhi Pang ,  Rohan U. Mandrekar

IPC: H01L25/16 ,  G01R31/64 ,  H01L23/525 ,  H01L21/66 ,  H01L49/02

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

公开(公告)号：US20210202332A1

公开(公告)日：2021-07-01

申请号：US16729094

申请日：2019-12-27

Applicant: Apple Inc.

Inventor： Kunzhong Hu ,  Chonghua Zhong ,  Jiongxin Lu ,  Jun Zhai

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/28 ,  H01L23/488 ,  H01L23/00 ,  H01L21/56

Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. In an embodiment, the interposer is stacked on the package substrate and joined with a conductive film. In an embodiment the interposer is formed on the package substrate during a reconstitution sequence.

公开(公告)号：US20210043511A1

公开(公告)日：2021-02-11

申请号：US17080609

申请日：2020-10-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20180204820A1

公开(公告)日：2018-07-19

申请号：US15408263

申请日：2017-01-17

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Se Young Yang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L25/0657 ,  G11C11/005 ,  G11C14/0018 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.

公开(公告)号：US09935076B1

公开(公告)日：2018-04-03

申请号：US15264087

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/77 ,  H01L21/66

CPC classification number: H01L21/77 ,  H01L24/17 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.