公开(公告)号：US08481412B2

公开(公告)日：2013-07-09

申请号：US12893399

申请日：2010-09-29

申请人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

发明人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

摘要翻译： 用于在衬底上形成互连的方法和装置包括在超低k电介质中的蚀刻图案，并且使用主动能量辅助烘烤从超低k电介质去除湿气。 在活性能量辅助烘烤期间，在约300至约400摄氏度的温度下，超低k电介质被加热并暴露于仅具有大于400nm波长的光约1至约20分钟。 活性能量辅助烘烤在湿清洗或化学机械抛光之后进行，或两者都进行。

公开(公告)号：US20130052755A1

公开(公告)日：2013-02-28

申请号：US13219317

申请日：2011-08-26

申请人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/66

CPC分类号： H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

公开(公告)号：US20120306098A1

公开(公告)日：2012-12-06

申请号：US13571276

申请日：2012-08-09

申请人： Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Joung-Wei Liou ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L23/522 ,  H01L21/02348 ,  H01L21/31 ,  H01L21/76825 ,  H01L23/53295 ,  H01L23/562 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05553 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.

摘要翻译： 提供了包括反射金属焊盘的集成电路结构。 集成电路结构包括半导体衬底; 覆盖半导体衬底的第一低k电介质层，其中第一低k电介质层是顶部低k电介质层; 位于第一低k电介质层下面的第二低k电介质层; 以及第二低k电介质层中的反射金属焊盘。

公开(公告)号：US20120001262A1

公开(公告)日：2012-01-05

申请号：US12829664

申请日：2010-07-02

申请人： Huang Soon Kang ,  Han-Hsin Kuo ,  Chi-Ming Yang ,  Shwang-Ming Jeng ,  Chin-Hsiang Lin

发明人： Huang Soon Kang ,  Han-Hsin Kuo ,  Chi-Ming Yang ,  Shwang-Ming Jeng ,  Chin-Hsiang Lin

IPC分类号： H01L29/78 ,  B24B7/00 ,  H01L21/306

CPC分类号： H01L23/5386 ,  H01L21/02074 ,  H01L21/28079 ,  H01L21/67011 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

摘要翻译： 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。

公开(公告)号：US20110223759A1

公开(公告)日：2011-09-15

申请号：US12724229

申请日：2010-03-15

申请人： Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.

摘要翻译： 在互连结构的形成中，在电介质层中形成金属特征。 使用前体和包含碳作为前体的碳源气体在金属特征和电介质层上形成蚀刻停止层（ESL）。 碳源气体不含二氧化碳（CO2）。 前体选自基本上由1-甲基硅烷（1MS），2-甲基硅烷（2MS），3-甲基硅烷（3MS），4-甲基硅烷（4MS）及其组合组成的组。

公开(公告)号：US20100120253A1

公开(公告)日：2010-05-13

申请号：US12547232

申请日：2009-08-25

申请人： Shwang-Ming Jeng ,  Kin-Weng Wang ,  Hsin-Yi Tsai ,  Keng-Chu Lin ,  Chung-Chi Ko

发明人： Shwang-Ming Jeng ,  Kin-Weng Wang ,  Hsin-Yi Tsai ,  Keng-Chu Lin ,  Chung-Chi Ko

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L2221/1063

摘要： Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.

摘要翻译： 用于改善半导体器件中的通孔或沟槽形成中的后蚀刻的方法。 优选实施例包括在初始蚀刻之后在电介质膜上形成覆盖层，以在电介质膜中形成特征，随后进行另外的蚀刻和回蚀处理步骤。 重新覆盖方法为底层膜提供保护，并防止蚀刻后的膜损伤。 通过使用本发明的方法维持均匀的特征轮廓并获得临界尺寸均匀性。 时间依赖介电击穿性能提高。

公开(公告)号：US07626245B2

公开(公告)日：2009-12-01

申请号：US11968324

申请日：2008-01-02

申请人： Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

发明人： Fang-Wen Tsai ,  Kuan-Chen Wang ,  Keng-Chu Lin ,  Chih-Lung Lin ,  Shwang-Ming Jeng

IPC分类号： H01L23/58 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

摘要翻译： 用于高级互连的极低k（ELK）电介质膜方案包括上ELK电介质层和具有不同折射率的下ELK电介质。 上部ELK介电层的折射率大于下部ELK介电层的折射率。

公开(公告)号：US10312107B2

公开(公告)日：2019-06-04

申请号：US13228011

申请日：2011-09-08

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/311 ,  H01L21/321 ,  H01L21/768

摘要： A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

公开(公告)号：US09196551B2

公开(公告)日：2015-11-24

申请号：US13219317

申请日：2011-08-26

申请人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

摘要翻译： 一种方法包括蚀刻晶片上的低k电介质层以在低k电介质层中形成开口。 测量晶片中有害物质的量以获得测量结果。 响应于测量结果确定用于烘烤晶片的工艺条件。 使用确定的工艺条件烘烤晶片。

公开(公告)号：US20130062774A1

公开(公告)日：2013-03-14

申请号：US13228011

申请日：2011-09-08

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/321 ,  H01L21/76811 ,  H01L21/76813

摘要： A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

摘要翻译： 一种方法包括在低k电介质层上形成金属硬掩模。 形成金属硬掩模的步骤包括沉积金属硬掩模的子层，并对金属硬掩模的子层进行等离子体处理。 将金属硬掩模图案化以形成开口。 蚀刻低k电介质层以形成沟槽，其中使用金属硬掩模作为蚀刻掩模进行蚀刻步骤。