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102 条记录 (耗时 0.028 秒)

    DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR
    31.
    发明申请
    DAMASCENE COPPER WIRING OPTICAL IMAGE SENSOR 有权
    DAMASCENE铜接线光学图像传感器

    公开(公告)号：US20070114622A1

    公开(公告)日：2007-05-24

    申请号：US11623977

    申请日：2007-01-17

    申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

    发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Anthony Stamper

    IPC分类号： H01L29/82

    CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a inner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合具有改进的厚度均匀性的内部层间电介质叠层，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

    CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM
    32.
    发明申请
    CMOS IMAGER WITH CU WIRING AND METHOD OF ELIMINATING HIGH REFLECTIVITY INTERFACES THEREFROM 失效
    具有CU布线的CMOS成像器和消除其高反射性接口的方法

    公开(公告)号：US20080108170A1

    公开(公告)日：2008-05-08

    申请号：US11959841

    申请日：2007-12-19

    申请人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

    发明人： James Adkisson ,  Jeffrey Gambino ,  Mark Jaffe ,  Robert Leidy ,  Richard Rassel ,  Anthony Stamper

    IPC分类号： H01L21/04

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES
    34.
    发明申请
    LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES 有权
    低功耗超低功耗，小型设备结构

    公开(公告)号：US20070122957A1

    公开(公告)日：2007-05-31

    申请号：US11164651

    申请日：2005-11-30

    申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

    发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Jeffrey Gambino ,  Shih-Fen Huang ,  Edward Nowak ,  Anthony Stamper

    IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

    摘要翻译： 为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或 接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化 的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

    PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION
    35.
    发明申请
    PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION 有权
    使用集中处理和至少部分严格封装防止金属损坏

    公开(公告)号：US20060292863A1

    公开(公告)日：2006-12-28

    申请号：US11160465

    申请日：2005-06-24

    申请人： Jeffrey Gambino ,  Anthony Stamper

    发明人： Jeffrey Gambino ,  Anthony Stamper

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76865

    摘要： Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a metal surface in a bottom of the opening, where the opening forming step occurs in a tool including at least one clustered chamber. An at least partially sacrificial encapsulation layer is then formed on the exposed metal surface in the tool to prevent reaction of the exposed metal surface with the ambient. Exposure of the metal is thereby prevented.

    摘要翻译： 公开了用于在半导体加工期间防止金属暴露的金属封装的方法。 在一个实施例中，该方法包括在露出开口底部的金属表面的结构中形成开口，其中开口形成步骤发生在包括至少一个聚集室的工具中。 然后在工具中的暴露的金属表面上形成至少部分牺牲的封装层，以防止暴露的金属表面与环境的反应。 从而防止了金属的暴露。

    METHOD AND STRUCTURE TO PREVENT CIRCUIT NETWORK CHARGING DURING FABRICATION OF INTEGRATED CIRCUITS
    39.
    发明申请
    METHOD AND STRUCTURE TO PREVENT CIRCUIT NETWORK CHARGING DURING FABRICATION OF INTEGRATED CIRCUITS 失效
    在整合电路制造过程中防止电路网络充电的方法和结构

    公开(公告)号：US20070166848A1

    公开(公告)日：2007-07-19

    申请号：US11687711

    申请日：2007-03-19

    申请人： Jeffrey Gambino ,  Kirk Peterson

    发明人： Jeffrey Gambino ,  Kirk Peterson

    IPC分类号： H01L21/00 ,  H01L21/82

    CPC分类号： H01L27/1203 ,  H01L23/5256 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.

    摘要翻译： 集成电路及其制造方法。 该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络， 更多数据网络及其组合。