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    Method and system to detect errors in computer systems by using state tracking
    31.
    发明授权
    Method and system to detect errors in computer systems by using state tracking 有权
    通过使用状态跟踪来检测计算机系统中的错误的方法和系统

    公开(公告)号：US07752497B2

    公开(公告)日：2010-07-06

    申请号：US12206996

    申请日：2008-09-09

    申请人： Joachim von Buttlar ,  Janet R. Easton ,  Kenneth J. Oakes ,  Andrew W. Piechowski ,  Martin Taubert ,  John S. Trotter

    发明人： Joachim von Buttlar ,  Janet R. Easton ,  Kenneth J. Oakes ,  Andrew W. Piechowski ,  Martin Taubert ,  John S. Trotter

    IPC分类号： G06F11/00

    CPC分类号： G06F11/362

    摘要： Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

    摘要翻译： 公开了一种用于检测包括处理单元的计算机系统中的错误的方法和系统，该处理单元执行改变项目的任务。 该方法包括以下步骤：向处理单元分配任务控制块，并且使用任务控制块来跟踪由处理单元改变的项目。 该方法还包括步骤：在定义的时间，检查任务控制块以识别由处理单元改变的项目，以及检查所识别的项目的状态，以确定这些状态是否正确。 本发明的优选实施例在出现时（如果可能的话）检测到错误，并且利用允许在导致后续问题之前检测错误的简单和周期性一致性检查（例如，在指定的代码点）的基础设施。

    METHOD AND SYSTEM TO DETECT ERRORS IN COMPUTER SYSTEMS BY USING STATE TRACKING
    32.
    发明申请
    METHOD AND SYSTEM TO DETECT ERRORS IN COMPUTER SYSTEMS BY USING STATE TRACKING 有权
    通过状态跟踪来检测计算机系统中的错误的方法和系统

    公开(公告)号：US20090006892A1

    公开(公告)日：2009-01-01

    申请号：US12206996

    申请日：2008-09-09

    申请人： Joachim von Buttlar ,  Janet R. Easton ,  Kenneth J. Oakes ,  Andrew W. Piechowski ,  Martin Taubert ,  John S. Trotter

    发明人： Joachim von Buttlar ,  Janet R. Easton ,  Kenneth J. Oakes ,  Andrew W. Piechowski ,  Martin Taubert ,  John S. Trotter

    IPC分类号： G06F11/00

    CPC分类号： G06F11/362

    摘要： Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being changed by the processing unit. The method comprises the further steps of at defined times, checking the task control block to identify items being changed by the processing unit, and checking the states of said identified items to determine if those states are correct. The preferred embodiment of the invention detects an error when it arises (where possible), and utilizes an infrastructure that allows simple and periodic consistency checks (for example, at designated code points) that detect the error before it causes follow-on problems.

    摘要翻译： 公开了一种用于检测包括处理单元的计算机系统中的错误的方法和系统，该处理单元执行改变项目的任务。 该方法包括以下步骤：向处理单元分配任务控制块，并且使用任务控制块来跟踪由处理单元改变的项目。 该方法还包括步骤：在定义的时间，检查任务控制块以识别由处理单元改变的项目，以及检查所识别的项目的状态，以确定这些状态是否正确。 本发明的优选实施例在出现时（如果可能的话）检测到错误，并且利用允许在导致后续问题之前检测错误的简单和周期性一致性检查（例如，在指定的代码点）的基础设施。

    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS
    33.
    发明申请
    MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS 有权
    管理非专用中断硬件环境中的输入/输出中断

    公开(公告)号：US20080235425A1

    公开(公告)日：2008-09-25

    申请号：US12125963

    申请日：2008-05-23

    申请人： Brenton F. Belmar ,  Janet R. Easton ,  Tan Lu ,  Damian L. Osisek ,  Richard P. Tarcza ,  Leslie W. Wyman

    发明人： Brenton F. Belmar ,  Janet R. Easton ,  Tan Lu ,  Damian L. Osisek ,  Richard P. Tarcza ,  Leslie W. Wyman

    IPC分类号： G06F13/24

    CPC分类号： G06F9/4812 ,  G06F9/45537

    摘要： Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.

    摘要翻译： 输入/输出中断在不使用专用每个客户机中断硬件来呈现中断的计算环境中进行管理。 环境中可分派的访客程序直接接收I / O中断，无需管理程序干预。 这通过使用存储在存储器中并与每个客户程序相关联的一个或多个中断控制来促进。 对于目前不可分发的客户程序，可以为客人发布中断，并可以对通知程序进行汇总。 然后管理程序可以在单个调用中处理多个客人的多个通知。

    Intelligent interrupt with hypervisor collaboration
    35.
    发明授权
    Intelligent interrupt with hypervisor collaboration 失效
    智能中断与管理程序协作

    公开(公告)号：US06880021B2

    公开(公告)日：2005-04-12

    申请号：US09966232

    申请日：2001-09-28

    申请人： Janet R. Easton ,  Jeffrey P. Kubala ,  Donald W. Schmidt

    发明人： Janet R. Easton ,  Jeffrey P. Kubala ,  Donald W. Schmidt

    IPC分类号： G06F13/24 ,  G06F3/00

    CPC分类号： G06F13/24

    摘要： An apparatus, method and program product for controlling the transfer of data in a data processing system having a processor handling an I/O request in an I/O operation, main storage controlled by the processor for storing data, and one or more I/O devices for sending data to or receiving data from said main storage. The apparatus includes a vector mechanism operable to register I/O requests by the devices to send or receive data from said main storage. A dispatcher is included which is operable to poll the vector mechanism to determine if there is an outstanding I/O request. An override bit has a first condition when an immediate interrupt is to be sent to the processor for handling an I/O request from the I/O device(s), and a second condition when the dispatcher is to poll the vector mechanism to determine if there is an outstanding I/O request. The override bit is set to its first condition or reset to its second condition by the processor.

    摘要翻译： 一种用于控制数据处理系统中的数据传输的装置，方法和程序产品，所述数据处理系统具有处理I / O操作中的I / O请求的处理器，由处理器控制的用于存储数据的主存储器，以及一个或多个I / O设备，用于向所述主存储器发送数据或从所述主存储器接收数据。 该装置包括一个向量机构，可操作用于寄存设备的I / O请求，以从所述主存储器发送或接收数据。 包括调度器，其可操作以轮询向量机制以确定是否存在未完成的I / O请求。 当将即时中断发送到处理器以处理来自I / O设备的I / O请求时，覆盖位具有第一条件，当调度器要轮询向量机制以确定 如果有一个未完成的I / O请求。 覆盖位被设置为其第一个条件或由处理器重置为其第二个条件。

    Low overhead I/O interrupt
    37.
    发明授权
    Low overhead I/O interrupt 有权
    低开销I / O中断

    公开(公告)号：US06754738B2

    公开(公告)日：2004-06-22

    申请号：US09966633

    申请日：2001-09-28

    申请人： Frank W. Brice, Jr. ,  Janet R. Easton ,  Steven G. Glassen ,  Kenneth J. Oakes ,  Donald W. Schmidt ,  Harry M. Yudenfriend

    发明人： Frank W. Brice, Jr. ,  Janet R. Easton ,  Steven G. Glassen ,  Kenneth J. Oakes ,  Donald W. Schmidt ,  Harry M. Yudenfriend

    IPC分类号： G06F1320

    CPC分类号： G06F9/4825 ,  G06F13/24

    摘要： An apparatus, method and program product for sending data to or receiving data from one or more I/O devices in an I/O operation with a main storage controlled by a processor in a data processing system. The apparatus includes a time-of-day (TOD) register for containing a TOD value, a clock for containing a current TOD value, and a summary register having a first condition when any one of said devices requests an I/O operation and a second condition when no devices have an outstanding I/O request, each device having an outstanding I/O request sets the summary register to its first condition only when the summary register is in its second condition, and further places the current TOD value in the TOD register. A checking program determines if a specified time delay has been exceeded between the value in said TOD register and the current TOD for each requested I/O operation. The checking program drives an interrupt to the processor when the specified time delay has been exceeded.

    摘要翻译： 一种用于在I / O操作中从一个或多个I / O设备向数据处理系统中由处理器控制的主存储器发送数据或从其接收数据的装置，方法和程序产品。 该装置包括用于包含TOD值的时间（TOD）寄存器，用于包含当前TOD值的时钟，以及当所述设备中的任何一个请求I / O操作时具有第一状态的汇总寄存器，以及 当没有设备具有未完成的I / O请求的第二个条件时，每个具有未完成的I / O请求的设备仅在汇总寄存器处于其第二条件时才将汇总寄存器设置为其第一个条件，并且将当前的TOD值进一步置于 TOD寄存器。 检查程序确定在所述TOD寄存器中的值和每个所请求的I / O操作的当前TOD之间是否已经超过指定的时间延迟。 当超过指定的时间延迟时，检查程序将驱动中断给处理器。

    Computer program device and product for timely processing of data using a queued direct input-output device
    38.
    发明授权
    Computer program device and product for timely processing of data using a queued direct input-output device 有权
    计算机程序设备和产品，用于使用排队的直接输入输出设备及时处理数据

    公开(公告)号：US06345326B1

    公开(公告)日：2002-02-05

    申请号：US09252730

    申请日：1999-02-19

    申请人： Michael E. Baskey ,  Frank W. Brice ,  Daniel F. Casper ,  Janet R. Easton ,  Steven G. Glassen ,  Eugene P. Hefferon ,  Bruce H. Ratcliff ,  Arthur J. Stagg ,  Leslie W. Wyman

    发明人： Michael E. Baskey ,  Frank W. Brice ,  Daniel F. Casper ,  Janet R. Easton ,  Steven G. Glassen ,  Eugene P. Hefferon ,  Bruce H. Ratcliff ,  Arthur J. Stagg ,  Leslie W. Wyman

    IPC分类号： G06F1300

    CPC分类号： H04L25/05

    摘要： A computer program device and product is provided for timely processing of data. The computer program device comprises a program storage device readable by a digital processing apparatus and a program means including instructions executable by the digital processing apparatus by designating at least one set of queues in the queuing mechanism as input queues and another as output queues; issuing a signal adapter instruction to provide initiative to check content of any or all queues in the queuing mechanism; specifying initiate-output or initiate-input appropriately by means of said signal adapter instruction to cause associated adapter to asynchronously process said output or input queues; and causing synchronization by means of said signal adapter instruction by signaling the associated data queues to update all entries in order to render them current. The computer program product is for use with a computer system and has a main storage in processing communication with an interface element having adapters for storing a queuing mechanism storing data. It comprises of a data storage device including a computer usable medium having computer readable program means for ensuring proper and timely processing of data, for dedicating at least one set of queues of the queuing mechanism as input queues and another set as output queues and for generating a signal adapter instruction designated to provide initiative to check content of any or all queues in said queuing mechanism.

    摘要翻译： 提供计算机程序设备和产品以及时处理数据。 计算机程序设备包括可由数字处理设备读取的程序存储设备和包括可由数字处理设备执行的指令的程序设备，通过将排队机构中的至少一组队列指定为输入队列，另一个作为输出队列; 发出信号适配器指令，提供主动检查排队机构中任何或所有队列的内容; 通过所述信号适配器指令适当地指定启动输出或启动输入，以使相关联的适配器异步地处理所述输出或输入队列; 并通过所述信号适配器指令通过发信号通知相关的数据队列来更新所有条目以使其成为当前状态，从而进行同步。 计算机程序产品用于计算机系统，并且具有处理与具有用于存储存储数据的排队机构的适配器的接口元件的通信的主存储器。 它包括数据存储装置，包括具有计算机可读程序装置的计算机可用介质的计算机可用介质，用于确保适当和及时地处理数据，用于将排队机构的至少一组队列作为输入队列，另一组作为输出队列，并用于生成 指定用于提供主动检查所述排队机构中的任何或所有队列的内容的信号适配器指令。

    Dequeue operation using mask vector to manage input/output interruptions
    39.
    发明授权
    Dequeue operation using mask vector to manage input/output interruptions 失效
    使用掩码向量的出队操作来管理输入/输出中断

    公开(公告)号：US08762615B2

    公开(公告)日：2014-06-24

    申请号：US13332427

    申请日：2011-12-21

    申请人： Janet R. Easton ,  Norbert Hagspiel ,  Bernd Nerz

    发明人： Janet R. Easton ,  Norbert Hagspiel ,  Bernd Nerz

    IPC分类号： G06F9/48

    CPC分类号： G06F13/24

    摘要： A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset.

    摘要翻译： 发出命令以重置一个或多个待处理的中断指示符并仲裁中断的所有权。 响应于接收到该命令的处理器，检查所选待处理的中断指示符。 如果未设置所选待处理的中断指示符，则会检查另一个未决中断指示符，而不是提供否定响应并重新发出命令。 以这种方式，一个出队命令可以取代多个出队命令，减少了离开和重新进入中断处理程序的开销。 对于没有待复位的待处理中断指示符的情况，保留一个否定的响应。