公开(公告)号：US20240006011A1

公开(公告)日：2024-01-04

申请号：US18467996

申请日：2023-09-15

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C2029/0407 ,  G11C29/4401 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US20230384930A1

公开(公告)日：2023-11-30

申请号：US18447031

申请日：2023-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Cristian P. MASGRAS

IPC: G06F3/06

CPC classification number: G06F3/0601 ,  G06F3/0604 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

公开(公告)号：US20230378958A1

公开(公告)日：2023-11-23

申请号：US18362704

申请日：2023-07-31

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: H03K19/1776 ,  G11C13/00 ,  H03K19/17784 ,  G11C11/16 ,  H03K19/17724 ,  G06F21/78

CPC classification number: H03K19/1776 ,  G11C13/0069 ,  H03K19/17784 ,  G11C11/1675 ,  H03K19/17724 ,  G06F21/78

Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

公开(公告)号：US20230238039A1

公开(公告)日：2023-07-27

申请号：US18189738

申请日：2023-03-24

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: 1. The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US20220139488A1

公开(公告)日：2022-05-05

申请号：US17512392

申请日：2021-10-27

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Jason JANESKY ,  Han Kyu LEE ,  Hamid ALMASI ,  Pedro SANCHEZ ,  Cristian P. MASGRAS ,  Iftekhar RAHMAN ,  Sumio IKEGAWA ,  Sanjeev AGGARWAL ,  Dimitri HOUSSAMEDDINE ,  Frederick Charles NEUMEYER

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/18

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：US20190221247A1

公开(公告)日：2019-07-18

申请号：US16251882

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM

IPC: G11C11/16 ,  G11C11/4094 ,  G11C7/12 ,  G06F11/10

Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.

公开(公告)号：US20190221242A1

公开(公告)日：2019-07-18

申请号：US16252067

申请日：2019-01-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM ,  Frederick NEUMEYER

IPC: G11C5/14 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C5/147 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/224 ,  H01L27/228 ,  H01L43/08

Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.

公开(公告)号：US20190214070A1

公开(公告)日：2019-07-11

申请号：US16358414

申请日：2019-03-19

Applicant: Everspin Technologies, Inc.

Inventor： Jason JANESKY ,  Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Mark DEHERREA

IPC: G11C11/16 ,  G11C17/16 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

公开(公告)号：US20190156878A1

公开(公告)日：2019-05-23

申请号：US16217185

申请日：2018-12-12

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20190088306A1

公开(公告)日：2019-03-21

申请号：US16192344

申请日：2018-11-15

Applicant: Everspin Technologies, Inc.

Inventor： Thomas ANDRE ,  Syed M. ALAM

IPC: G11C11/16 ,  G06F12/0806 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0879 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/419 ,  G11C11/4094 ,  G11C11/56

Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.