公开(公告)号：US10475693B1

公开(公告)日：2019-11-12

申请号：US16002403

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.

公开(公告)号：US20190326177A1

公开(公告)日：2019-10-24

申请号：US15958593

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Haiting Wang ,  Hong Yu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66

Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

公开(公告)号：US10121788B1

公开(公告)日：2018-11-06

申请号：US15873006

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/02 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US09553194B1

公开(公告)日：2017-01-24

申请号：US14812653

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Zhenyu Hu ,  Hong Yu ,  Jinping Liu

IPC: H01L29/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7853 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/66795

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract translation: 一种方法可以包括执行蚀刻工艺以限定具有第一深度的翅片沟槽，第一深度小于翅片的目标高度。 方法还可以包括形成层以保护限定翅片沟槽的侧壁。 方法还可以包括执行第二蚀刻工艺以增加散热片沟槽的深度。

公开(公告)号：US09455198B1

公开(公告)日：2016-09-27

申请号：US14676034

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Lun Zhao ,  Richard J. Carter ,  Xusheng Wu

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Abstract translation: 本文公开的一种说明性方法包括除去第一图案化掩模层中的多个第一特征中的至少一个但不是全部的，以便限定经修改的第一图案化掩模层，其中去除的第一特征 对应于将形成最终隔离结构的位置，通过经修改的第一图案化掩模层执行蚀刻工艺，以在衬底中形成初始隔离沟槽，以及通过修改的第一图案化掩模层执行另一蚀刻工艺，由此限定 在衬底中的多个翅片形成沟槽并且延伸初始隔离沟槽的深度，以便限定用于最终隔离结构的最终隔离沟槽。

公开(公告)号：US09362176B2

公开(公告)日：2016-06-07

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhao Lun ,  Zhenyu Hu ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US09324841B2

公开(公告)日：2016-04-26

申请号：US14049848

申请日：2013-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract translation: 本发明的实施例提供了用于制造诸如finFET的场效应晶体管的改进方法。 应力区域用于增加载流子迁移率。 然而，诸如沉积可流动氧化物和退火的后续过程可能损害应力区域，减少了所引起的应力量。 本发明的实施例在可流动的氧化物沉积和退火之前在应力区域上提供硅或氧化硅的保护层。

公开(公告)号：US09093561B2

公开(公告)日：2015-07-28

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Huang Liu ,  Lun Zhao ,  Richard J. Carter

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/84

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150200260A1

公开(公告)日：2015-07-16

申请号：US14156745

申请日：2014-01-16

Applicant: GlobalFoundries Inc.

Inventor： Hong Yu ,  Jinping Liu

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments of the present invention provide an improved contact formation process for a finFET. Epitaxial semiconductor regions are formed on the fins. A contact etch stop layer (CESL) is deposited on the epitaxial regions. A nitride-oxide conversion process converts a portion of the nitride CESL into oxide. The oxide-converted portions are removed using a selective etch process, and a fill metal is deposited which is in direct physical contact with the epitaxial regions. Damage, such as gouging, of the epitaxial regions is minimized during this process, resulting in an improved contact for finFETs.

Abstract translation: 本发明的实施例提供了一种用于finFET的改进的接触形成方法。 在翅片上形成外延半导体区域。 接触蚀刻停止层（CESL）沉积在外延区域上。 氮化物 - 氧化物转换处理将氮化物CESL的一部分转化为氧化物。 使用选择性蚀刻工艺去除氧化物转化的部分，并且沉积与外延区域直接物理接触的填充金属。 在该过程期间，使外延区域的损耗（例如气蚀）最小化，导致finFET的接触改善。

公开(公告)号：US09024368B1

公开(公告)日：2015-05-05

申请号：US14079757

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Bingwu Liu ,  Puneet Khanna ,  Lun Zhao

IPC: H01L29/76 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract translation: 鳍型晶体管制造方法和结构被提供具有延伸的嵌入应力元件。 所述方法包括例如：提供在衬底上延伸的翅片上延伸的栅极结构; 使用各向同性蚀刻和各向异性蚀刻在翅片内形成延伸空腔，其中延伸空腔部分地削弱了栅极结构，并且其中使用各向同性蚀刻和各向异性蚀刻将扩展腔加深到底切栅结构下方的翅片 ; 以及至少部分地在所述延伸空腔内形成嵌入的应力元件，包括在所述栅极结构下方。