公开(公告)号：US09847390B1

公开(公告)日：2017-12-19

申请号：US15434205

申请日：2017-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66742 ,  H01L29/78684

Abstract: This disclosure relates to forming a wrap-around contact on a nanosheet transistor, the method including: forming an etch-stop layer over a continuous outer surface of a raised source/drain (S/D) region of the nanosheet transistor; forming a sacrificial layer over the etch-stop layer, the etch-stop layer including a different material than the sacrificial layer; depositing a dielectric layer over the sacrificial layer; removing an upper portion of the dielectric layer to expose a portion of the sacrificial layer; removing the sacrificial layer selective to the etch-stop layer; and depositing a conductor in the removed upper portion of the dielectric layer to form a wrap-around contact and a second contact.

公开(公告)号：US09837404B2

公开(公告)日：2017-12-05

申请号：US15082242

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US20170309714A1

公开(公告)日：2017-10-26

申请号：US15639095

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

公开(公告)号：US09799748B1

公开(公告)日：2017-10-24

申请号：US15398335

申请日：2017-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a stack of semiconductor material layers above a substrate. The stack includes at least one first semiconductor material layer and at least one second semiconductor material layer. A first etching process is performed on the stack to define cavities. The cavities expose end portions of the first and second semiconductor material layers. Portions of the first semiconductor material layer are removed to define end recesses. A layer of insulating material is formed in the end recesses and at least partially fills the cavities. A second etching process is performed on the stack to remove end portions of the at least one second semiconductor material layer and to remove portions of the layer of insulating material in the cavities not disposed between the first and second semiconductor material layers so as to form inner spacers on ends of the at least one first semiconductor material layer.

公开(公告)号：US20170294338A1

公开(公告)日：2017-10-12

申请号：US15630546

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US09780208B1

公开(公告)日：2017-10-03

申请号：US15212755

申请日：2016-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US09735242B2

公开(公告)日：2017-08-15

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/41 ,  H01L29/417 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

公开(公告)号：US09735061B1

公开(公告)日：2017-08-15

申请号：US15014150

申请日：2016-02-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Min-gyu Sung ,  Ruilong Xie ,  Chanro Park

IPC: H01L21/44 ,  H01L21/31 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/82345 ,  H01L21/28185 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed. Embodiments include providing an interfacial-layer on a semiconductor substrate; forming a first high-k dielectric-layer on the interfacial-layer; forming a second high-k dielectric-layer and a first cap-layer, respectively, on the first high-k dielectric-layer; removing the second high-k dielectric and first cap layers in first and second regions; forming a second cap-layer on the first high-k dielectric-layer in the first and second regions and on the first cap-layer in a third region; performing an annealing process; removing the second cap-layer from all regions and the first cap-layer from the third region; forming a third high-k dielectric-layer over all regions; forming a work-function composition-layer and a barrier-layer on the third high-k dielectric-layer in all regions; removing the barrier-layer from the first region; and forming a gate electrode over all regions.

公开(公告)号：US09722053B1

公开(公告)日：2017-08-01

申请号：US15075557

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US20170207122A1

公开(公告)日：2017-07-20

申请号：US15470006

申请日：2017-03-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2221/1026 ,  H01L2221/1036

Abstract: An integrated circuit product includes two laterally spaced-apart transistors, wherein each of the two laterally spaced-apart transistors includes a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to sidewalls of the gate structure. A source/drain region is positioned between the two laterally spaced-apart transistors, and a conformal etch stop layer is positioned on and in contact with an upper surface of the source/drain region and on and in contact with a sidewall surface of the sidewall spacer of each of the two laterally spaced-apart transistors. A self-aligned conductive contact extends through an opening in the conformal etch stop layer and is conductively coupled to the source/drain region.