公开(公告)号：US20150311082A1

公开(公告)日：2015-10-29

申请号：US14261823

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Gabriel Padron Wells ,  Andre P. Labonte ,  Jing Wan

IPC: H01L21/28 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L29/41775 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: Provided are approaches for forming gate and source/drain (S/D) contacts. Specifically, a gate contact opening is formed over at least one of a set of gate structures, a set of S/D contact openings is formed over fins of the semiconductor device, and a metal material is deposited over the semiconductor device to form a gate contact within the gate contact opening and a set of S/D contacts within the set of S/D contact openings. In one approach, nitride remains between the gate contact and at least one of the S/D contacts. In another approach, the device includes merged gate and S/D contacts. This approach provides selective etching to partition areas where oxide will be further removed selectively to nitride to create cavities to metallize and create contact to the S/D, while isolation areas between contact areas are enclosed in nitride and do not get removed during the oxide etch.

Abstract translation: 提供了用于形成栅极和源极/漏极（S / D）触点的方法。 具体地说，栅极接触开口形成在一组栅极结构中的至少一个上，在半导体器件的鳍片之上形成一组S / D接触开口，并且在半导体器件上沉积金属材料以形成栅极 在门接触开口内接触一组S / D接触开口内的一组S / D接点。 在一种方法中，氮化物保留在栅极接触和至少一个S / D接触之间。 在另一种方法中，该装置包括合并门和S / D触点。 这种方法提供对分隔区域的选择性蚀刻，其中氧化物将被进一步选择性地去除氮化物以产生空穴以金属化并产生与S / D的接触，而接触区域之间的隔离区域被氮化物包围并且在氧化物蚀刻期间不被去除 。

公开(公告)号：US20150303295A1

公开(公告)日：2015-10-22

申请号：US14258279

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Xiang Hu ,  Jinping Liu ,  Gabriel Padron Wells ,  Andy Chih-Hung Wei ,  Guillaume Bouche ,  Cuiqin Xu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/51 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.

Abstract translation: 提供了在半导体器件（例如，FinFET器件）中形成一组接触开口的方法。 具体地，半导体器件包括形成在衬底中的一组翅片，形成在衬底上的栅极结构（例如，替换金属栅极（RMG））以及与栅极结构相邻的一组接触开口，该组接触 具有顶部和底部的开口，其中沿着栅极结构的长度的底部的宽度大于顶部的宽度。 半导体器件还包括形成在该组接触开口内的一组金属触头。

公开(公告)号：US20150303273A1

公开(公告)日：2015-10-22

申请号：US14258488

申请日：2014-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US10700170B2

公开(公告)日：2020-06-30

申请号：US14264240

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/161 ,  H01L29/16 ,  H01L23/482 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

公开(公告)号：US09842801B2

公开(公告)日：2017-12-12

申请号：US15155569

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/5329 ,  H01L29/0649

Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.

公开(公告)号：US09608086B2

公开(公告)日：2017-03-28

申请号：US14282257

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

公开(公告)号：US09461128B2

公开(公告)日：2016-10-04

申请号：US14963789

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L21/82 ,  H01L29/66 ,  H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

公开(公告)号：US09263325B1

公开(公告)日：2016-02-16

申请号：US14463801

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

Abstract translation: 本发明的实施例提供了一种在线结构后端切割牺牲金属线的方法。 牺牲Mx + 1线形成在金属Mx线之上。 在牺牲Mx + 1线上沉积并图案化切割光刻叠层并形成切割腔。 切割腔填充有介电材料。 选择性蚀刻工艺去除牺牲Mx + 1线，保留填充切割腔的电介质。 然后通过沉积除去牺牲Mx + 1线的金属形成预切割的金属线。 因此，本发明的实施例提供预切割金属线，并且不需要金属切割。 通过避免金属切割的需要，避免与金属切割相关的风险。

公开(公告)号：US09236437B2

公开(公告)日：2016-01-12

申请号：US14184830

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract translation: 本发明的实施例提供改进的接触形成方法。 公开了一种具有降低光刻要求的自对准接触方案。 这降低了源/漏极和栅极之间短路的风险，同时提供了改善的电路密度。 形成邻近门的腔，并且填充金属沉积在空腔中以形成接触条。 然后通过执行接触片的部分金属凹部来使用图案化掩模来形成更小的触点。

公开(公告)号：US20160005868A1

公开(公告)日：2016-01-07

申请号：US14320932

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Jing Wan ,  Dae-Han Choi

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Embodiments of the present invention provide a fin-type field effect transistor (finFET) with confined epitaxy. A protective layer is formed on a fin. The protective layer is recessed to expose the fin top. A fin cavity is formed in the fin. An epitaxial region is formed in the fin cavity. The epitaxial region has a confined portion and a diamond-shaped portion, resulting in increased epitaxial volume. The increased epitaxial volume can result in enhanced carrier mobility and improved device performance.

Abstract translation: 本发明的实施例提供了具有有限外延的翅片型场效应晶体管（finFET）。 在翅片上形成保护层。 保护层凹入以暴露翅片顶部。 翅片中形成翅片腔。 在翅片腔中形成外延区域。 外延区具有限制部分和菱形部分，导致增加的外延体积。 增加的外延体积可以导致增强的载流子迁移率和改进的器件性能。