公开(公告)号：US09236477B2

公开(公告)日：2016-01-12

申请号：US14181832

申请日：2014-02-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack O. Chu ,  Christos Dimitrakopoulos ,  Eric C. Harley ,  Judson R. Holt ,  Timothy J. McArdle ,  Matthew W. Stoker

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/0243 ,  H01L21/02447 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66795 ,  H01L29/7781

Abstract: Silicon-carbon alloy structures can be formed as inverted U-shaped structures around semiconductor fins by a selective epitaxy process. A planarization dielectric layer is formed to fill gaps among the silicon-carbon alloy structures. After planarization, remaining vertical portions of the silicon-carbon alloy structures constitute silicon-carbon alloy fins, which can have sublithographic widths. The semiconductor fins may be replaced with replacement dielectric material fins. In one embodiment, employing a patterned mask layer, sidewalls of the silicon-carbon alloy fins can be removed around end portions of each silicon-carbon alloy fin. An anneal is performed to covert surface portions of the silicon-carbon alloy fins into graphene layers. In one embodiment, each graphene layer can include only a horizontal portion in a channel region, and include a horizontal portion and sidewall portions in source and drain regions. If a patterned mask layer is not employed, each graphene layer can include only a horizontal portion.

Abstract translation: 硅碳合金结构可以通过选择性外延工艺形成为围绕半导体翅片的倒U形结构。 形成平坦化介电层以填充硅 - 碳合金结构之间的间隙。 在平坦化之后，硅 - 碳合金结构的剩余垂直部分构成可以具有亚光刻宽度的硅碳合金翅片。 半导体翅片可以用替换的介质材料翅片代替。 在一个实施例中，采用图案化掩模层，可以在每个硅 - 碳合金散热片的端部周围除去硅 - 碳合金散热片的侧壁。 执行退火以将硅碳合金翅片的表面部分隐藏成石墨烯层。 在一个实施例中，每个石墨烯层可以仅包括沟道区域中的水平部分，并且在源极和漏极区域中包括水平部分和侧壁部分。 如果不使用图案化掩模层，则每个石墨烯层可以仅包括水平部分。

公开(公告)号：US20190088766A1

公开(公告)日：2019-03-21

申请号：US15711410

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Jagar Singh ,  Judson R. Holt

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/06

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial sidewall spacer adjacent a sidewall spacer of a transistor and, with the sacrificial sidewall spacer in position, forming openings in an active layer of an SOI substrate adjacent the sacrificial sidewall spacer so as to thereby expose portions of a buried insulation layer of the SOI substrate. In this example, the method also includes performing an isotropic etching process to form recesses of any shape in the buried insulation layer, wherein the recesses extend laterally under a portion of the active layer, and forming an epi semiconductor material in at least the recesses in the buried insulation layer.

公开(公告)号：US10236343B2

公开(公告)日：2019-03-19

申请号：US15848591

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. Triyoso ,  Timothy J. McArdle ,  Judson R. Holt ,  Amy L. Child ,  George R. Mulfinger

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786

Abstract: A pFET includes a semiconductor-on-insulator (SOI) substrate; and a trench isolation within the SOI substrate, the trench isolation including a raised portion extending above an upper surface of the SOI substrate. A compressive channel silicon germanium (cSiGe) layer is over the SOI substrate. A strain retention member is positioned between at least a portion of the raised portion of the trench isolation and the compressive cSiGe layer. A gate and source/drain regions are positioned over the compressive cSiGe layer.

公开(公告)号：US20170179127A1

公开(公告)日：2017-06-22

申请号：US14974136

申请日：2015-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Shogo Mochizuki ,  Stephen W. Bedell

IPC: H01L27/092 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/155 ,  H01L29/66795

Abstract: An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium layer; and a dielectric between each fin in the set of fins; wherein each fin in a n-type field effect transistor (nFET) region further includes a strained silicon layer over the relaxed silicon germanium layer of each fin in the nFET region; wherein each fin in a p-type field effect transistor (pFET) region further includes a strained silicon germanium layer over the relaxed silicon germanium layer of each fin in the pFET region.

公开(公告)号：US20170148661A1

公开(公告)日：2017-05-25

申请号：US15425338

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L21/76 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having a top surface; (ii) refining the initial sub-assembly into a first trench-cut intermediate sub-assembly by removing material to form an upper tier of a trench extending downward from the top surface of the trench-defining layer, the upper tier of the trench including two lateral trench surfaces and a bottom trench surface; and (iii) refining the first trench-cut intermediate sub-assembly into a second trench-cut intermediate sub-assembly by selectively removing material in a downwards direction starting from the bottom surface of the trench to form a lower tier of the trench, with the selective removal of material leaving at least a first defect blocking member in the lower tier of the trench.

公开(公告)号：US09627480B2

公开(公告)日：2017-04-18

申请号：US14315385

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/786 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US09601565B2

公开(公告)日：2017-03-21

申请号：US14578523

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa A. Smith

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L29/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/2022 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/7605 ,  H01L21/76248 ,  H01L21/76294 ,  H01L29/0642 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” The epitaxial layer is grown epitaxially in the interior space of the trench. Each defect blocking member of the set of defect blocking members: (i) extends from a portion of trench surface into the interior space of the trench; and (ii) is located below a top surface of the epitaxial layer. The defect blocking member(s) are designed to arrest the propagation of generally-longitudinal defects in the epitaxial layer, as it is grown, where the generally-longitudinal defects are defects that propagate at least generally in the elongation direction of the trench.

公开(公告)号：US20170076991A1

公开(公告)日：2017-03-16

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

Abstract translation: 本公开的一个方面提供了一种不对称半导体器件。 不对称半导体器件可以包括：衬底; 以及设置在所述衬底上的鳍状场效应晶体管（FINFET），所述FINFET包括：设置在栅极附近的一组翅片; 第一外延区域，设置在所述一组鳍片上的源极区域上，所述第一外延区域具有第一高度; 以及设置在所述散热片组上的漏极区域上的第二外延区域，所述第二外延区域具有第二高度，其中所述第一高度与所述第二高度不同。

公开(公告)号：US20160181285A1

公开(公告)日：2016-06-23

申请号：US15054951

申请日：2016-02-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric C.T. Harley ,  Judson R. Holt ,  Yue Ke ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.

公开(公告)号：US20160163707A1

公开(公告)日：2016-06-09

申请号：US15016612

申请日：2016-02-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Eric C.T. Harley ,  Judson R. Holt ,  Gauri V. Karve ,  Yue Ke ,  Derrick Liu ,  Timothy J. McArdle ,  Shogo Mochizuki ,  Alexander Reznicek ,  Melissa Alyson Smith

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract translation: 本发明的实施例提供了一种外延生长FinFET的方法。 一种方法可以包括提供包括绝缘体和底层的半导体衬底; 使用外延生长在所述半导体衬底上形成沟道层; 将凹槽蚀刻到沟道层中并外延地再生沟道层上的一部分; 蚀刻通道层和底层以形成翅片; 形成栅极结构和一组间隔物; 将源漏区蚀刻到沟道层中; 以及在源极漏极区域中形成源极漏极材料。