公开(公告)号：US09922986B2

公开(公告)日：2018-03-20

申请号：US15155483

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L29/66 ,  H01L27/11531 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11519 ,  H01L29/43

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

公开(公告)号：US20170330889A1

公开(公告)日：2017-11-16

申请号：US15155483

申请日：2016-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11519 ,  H01L29/43

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A method includes providing a semiconductor structure having a gate structure arrangement provided over a substrate. The gate structure arrangement includes one or more first gate structures and has a first sidewall and a second sidewall on opposite sides of the gate structure arrangement. A second gate structure is formed including a first portion at the first sidewall, a second portion at the second sidewall and a third portion connecting the first and second portions. Each of the first, second and third portions of the second gate structure includes a first part over the gate structure arrangement and a second part over a portion of the substrate adjacent the gate structure arrangement. After the formation of the second gate structure, one or more sections of the second gate structure are removed, wherein the first and second portions of the second gate structure are separated from each other.

公开(公告)号：US20170317161A1

公开(公告)日：2017-11-02

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L49/02

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US09614003B1

公开(公告)日：2017-04-04

申请号：US14918736

申请日：2015-10-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Yu-Teh Chiang ,  Ran Yan

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a memory device structure including a wafer substrate, a magnetic tunnel junction (MTJ) formed by a first magnetic layer, a second magnetic layer, and a thin non-magnetic layer stacked along a first direction perpendicular to an upper surface of the wafer substrate above which the MTJ is formed, the non-magnetic layer being interposed between the first magnetic layer and the second magnetic layer, a first contact electrically coupled to the first magnetic layer, and a second contact electrically coupled to the second magnetic layer.

公开(公告)号：US09583640B1

公开(公告)日：2017-02-28

申请号：US14982028

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Sven Beyer ,  Carsten Grass ,  Tom Herrmann

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L29/7887 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

Abstract translation: 一种方法包括提供包括非易失性存储单元元件的半导体结构，所述非易失性存储单元元件包括在半导体材料上形成的浮置栅极，选择栅极和擦除栅极，所述选择栅极和擦除栅极被布置在所述浮置栅极的相对侧， 控制栅极绝缘材料层，在所述控制栅极绝缘材料层上方形成控制栅极材料层，执行在所述浮动栅极上形成控制栅极的第一图案化工艺，并且包括第一蚀刻工艺，所述第一蚀刻工艺选择性地去除 所述控制栅极材料层相对于所述控制栅极绝缘材料层的材料，并且执行对所述控制栅极绝缘材料层进行图案化的第二图案化工艺，所述图案化的控制栅极绝缘材料层覆盖所述半导体结构的不被 控制门。

公开(公告)号：US20160300928A1

公开(公告)日：2016-10-13

申请号：US14684559

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Peter Javorka ,  Ralf Richter

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6653

Abstract: A method of manufacturing a semiconductor device is provided including forming replacement gates over a semiconductor layer, forming sidewall spacers at sidewalls of the replacement gates, forming a dielectric layer in interspaces between the sidewall spacers of neighboring replacement gates, removing the replacement gates and sidewall spacers to form openings in the dielectric layer, and forming gate electrodes in the openings.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体层上形成替代栅极，在替换栅极的侧壁处形成侧壁间隔物，在相邻替代栅极的侧壁间隔件之间的间隙中形成介电层，去除替换栅极和侧壁间隔物 以在电介质层中形成开口，并在开口中形成栅电极。

公开(公告)号：US09406565B2

公开(公告)日：2016-08-02

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US20160005734A1

公开(公告)日：2016-01-07

申请号：US14856065

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract translation: 公开了一种集成电路产品，其包括具有第一PMOS有源区和第二PMOS有源区的半导体衬底，其中仅第二PMOS有源区具有形成于其上的锗锗层，形成在第一PMOS有源区和第二PMOS有源区之上的第一PMOS器件 PMOS有源区，第一PMOS器件具有第一栅极结构，以及形成在第二PMOS有源区中和上方的第二PMOS器件，第二PMOS器件具有设置在硅锗层上的第二栅极结构。

公开(公告)号：US09231045B2

公开(公告)日：2016-01-05

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US20150214116A1

公开(公告)日：2015-07-30

申请号：US14165107

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/8238 ,  H01L21/266 ,  H01L29/78 ,  H01L29/161 ,  H01L27/092 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7848

Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract translation: 提供一种形成半导体器件的方法，包括以下步骤：形成第一和第二PMOS晶体管器件，其中第一PMOS晶体管器件为低标准或高电压阈值晶体管器件，而第二PMOS晶体管器件为超高电压阈值晶体管器件 并且其中形成所述第一PMOS晶体管器件包括注入掺杂剂以形成所述第一PMOS晶体管器件的源极和漏极结，并且在注入所述掺杂剂之后执行所述第一PMOS晶体管器件的热退火，以及形成所述第二PMOS晶体管器件包括注入掺杂剂 以在第一PMOS晶体管器件进行热退火之后形成第二PMOS晶体管器件的源极和漏极结。