公开(公告)号：US20180075904A1

公开(公告)日：2018-03-15

申请号：US15557872

申请日：2015-04-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  Zhiyong Li ,  R. Stanley Williams

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: A memristive crossbar array is described. The crossbar array includes a number of row lines and a number of column lines intersecting the row lines to form a number of cross points. A number of memristor cells are coupled between the row lines and the column lines at the cross points. A memristor cell includes a memristive memory element to store information and multiple selectors electrically coupled to the memristive memory element. The multiple selectors are to provide access to the memristive memory element.

公开(公告)号：US20170358352A1

公开(公告)日：2017-12-14

申请号：US15535765

申请日：2014-12-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

公开(公告)号：US20170271009A1

公开(公告)日：2017-09-21

申请号：US15329845

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  John Paul Strachan ,  Gary Gibson ,  Warren Jackson

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/76

Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.

公开(公告)号：US10580473B2

公开(公告)日：2020-03-03

申请号：US16283513

申请日：2019-02-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  John Paul Strachan ,  Jianhua Yang ,  Miao Hu

IPC: G06F7/16 ,  G11C11/24 ,  G06G7/16 ,  G11C11/34

Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.

公开(公告)号：US10289423B2

公开(公告)日：2019-05-14

申请号：US15323945

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Vincent Nguyen ,  Chanh V. Hua ,  Ning Ge ,  Naveen Muralimanohar

IPC: G06F11/30 ,  G06F9/4401 ,  G06F1/3287

Abstract: A system management controller with a consolidated memory is disclosed. The example computing device includes a processor to host an operating system and a system memory to be used by the processor to execute instructions. The computing device also includes a management controller to enable out-of-band management of the computing device. The management controller includes a consolidated memory device. A first memory block of the consolidated memory device is used by the management controller as a working memory and a second memory block of the consolidated memory device is used for long-term storage of programming instructions.

公开(公告)号：US20190035463A1

公开(公告)日：2019-01-31

申请号：US16148468

申请日：2018-10-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Jianhua Yang ,  John Paul Strachan ,  Ning Ge

IPC: G11C13/00 ,  G06F17/16

Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

公开(公告)号：US09947405B2

公开(公告)日：2018-04-17

申请号：US15500075

申请日：2014-11-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Glen E. Montgomery ,  Ning Ge ,  Miao Hu ,  Jianhua Yang

IPC: G11C11/04 ,  G11C13/00 ,  G01J1/00 ,  G06G7/16

CPC classification number: G11C13/0069 ,  G01J1/00 ,  G06G7/16 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1006 ,  G11C11/1673 ,  G11C13/0021 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2013/0088 ,  G11C2213/77

Abstract: A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.

公开(公告)号：US09911788B2

公开(公告)日：2018-03-06

申请号：US15308923

申请日：2014-05-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  Zhiyong Li

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A selector with an oxide-based layer includes an oxide-based layer that has a first region and a second region. The first region contains a metal oxide in a first oxidation state, and the second region contains the metal oxide in a second oxidation state. The first region also forms a part of each of two opposite faces of the oxide-based layer.

公开(公告)号：US20180006449A1

公开(公告)日：2018-01-04

申请号：US15540192

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Richard J. Auletta ,  Ning Ge

IPC: H02H9/04 ,  H01L21/8234 ,  H01L45/00 ,  H01L27/02 ,  H01L27/092 ,  G11C13/00

CPC classification number: H02H9/046 ,  G11C13/004 ,  G11C13/0097 ,  G11C2029/5002 ,  H01L21/823475 ,  H01L27/0266 ,  H01L27/0288 ,  H01L27/092 ,  H01L45/1608

Abstract: In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.

公开(公告)号：US20170271409A1

公开(公告)日：2017-09-21

申请号：US15329913

申请日：2015-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  Katy Samuels ,  Minxian Max Zhang

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2418 ,  G11C11/1659 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625

Abstract: A resistive memory device includes a first electrode, a memristor coupled in electrical series with the first electrode, a second electrode coupled in electrical series with the memristor, a selector coupled in electrical series with the second electrode, and a third electrode coupled in electrical series with the selector. The memristor includes oxygen or nitrogen elements. The selector includes a composite dielectric material of a first dielectric material, a second dielectric material that is different from the first dielectric material, and a dopant material including a cation having a migration rate faster than the oxygen or the nitrogen elements of the memristor. The first dielectric material and the second dielectric material are present in a ratio ranging from 1:9 to 9:1, and a concentration of the dopant material in the composite dielectric material ranges from about 1% up to 50%.