公开(公告)号：US20070063276A1

公开(公告)日：2007-03-22

申请号：US11162663

申请日：2005-09-19

申请人： Jochen Beintner ,  Thomas Ludwig ,  Edward Nowak

发明人： Jochen Beintner ,  Thomas Ludwig ,  Edward Nowak

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

摘要翻译： 用于形成finFET的方法，结构和取向程序。 该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。 该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。 对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

公开(公告)号：US07091566B2

公开(公告)日：2006-08-15

申请号：US10717737

申请日：2003-11-20

申请人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

发明人： Huilong Zhu ,  Jochen Beintner ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7856

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. Each FET includes a device gate along one side of a semiconductor (e.g., silicon) fin and a back bias gate along an opposite of the fin. Back bias gate dielectric differs from the device gate dielectric either in its material and/or thickness. Device thresholds can be adjusted by adjusting back bias gate voltage.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 每个FET包括沿半导体（例如，硅）翅片的一侧的器件栅极和沿鳍片相对的背偏置栅极。 背偏置栅极电介质的不同之处在于器件栅极电介质的材料和/或厚度。 可以通过调整背偏置栅极电压来调整器件阈值。

公开(公告)号：US07091103B2

公开(公告)日：2006-08-15

申请号：US10314865

申请日：2002-12-09

申请人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

发明人： Jochen Beintner ,  Laertis Economikos ,  Michael Wise ,  Andreas Knorr

IPC分类号： H01L21/76 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/31055 ,  H01L27/1087 ,  H01L27/10894

摘要： CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

摘要翻译： 包含具有沟槽电容器的DRAM阵列的集成电路的CMP用氧化物填充沟槽，导致与周围的支撑结构中的浓度相比密集的氧化物结构的阵列，因此具有更高的负载。 保形层沉积在晶片上，增加阵列中的负载，但填充有效区域之间的空间。 覆盖蚀刻去除阵列和支撑体中的材料。 块蚀刻平衡阵列中的材料和支撑体的数量。 阵列中的补充氧化物沉积将结构之间的空间填充到几乎均匀的密度。

公开(公告)号：US20060157805A1

公开(公告)日：2006-07-20

申请号：US11266245

申请日：2005-11-04

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

IPC分类号： H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer. One or more other processing steps are preferably performed in completing the transistor.

摘要翻译： 形成缺口栅极MOSFET的结构和方法。 栅电介质形成在半导体衬底上的有源区的表面上。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物。 优选在完成晶体管时执行一个或多个其它处理步骤。

公开(公告)号：US20050277271A1

公开(公告)日：2005-12-15

申请号：US10709963

申请日：2004-06-09

申请人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

发明人： Jochen Beintner ,  Gary Bronner ,  Ramachandra Divakaruni ,  Byeong Kim

IPC分类号： C30B1/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/762 ,  H01L29/10 ,  H01L29/51 ,  H01L29/786

CPC分类号： H01L29/66628 ,  H01L21/76243 ,  H01L21/76251 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/938

摘要： The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

摘要翻译： 本发明提供了一种应变/ SGOI结构，其包括弛豫SiGe层的有源器件区，位于松弛SiGe层顶部的应变Si层，位于应变Si层的一部分顶部的凸起的源/漏区，以及 包括位于应变Si层的另一部分上的至少栅极电介质和栅极多晶硅的堆叠; 以及围绕有源器件区域的凸起的沟槽氧化物区域。 本发明还提供了一种形成这种结构的方法。 在本发明的方法中，在沟槽隔离形成之前形成栅极电介质，从而避免了与在栅极电介质形成之前形成沟槽氧化物的现有技术工艺相关的许多问题。

公开(公告)号：US06759291B2

公开(公告)日：2004-07-06

申请号：US10045499

申请日：2002-01-14

申请人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

发明人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

IPC分类号： H01L218234

CPC分类号： H01L27/10867

摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

摘要翻译： 一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。 沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。 控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。 此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。 唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。 衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形 形结构。 此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

公开(公告)号：US06607984B1

公开(公告)日：2003-08-19

申请号：US09597122

申请日：2000-06-20

申请人： Gill Yong Lee ,  Scott D. Halle ,  Jochen Beintner

发明人： Gill Yong Lee ,  Scott D. Halle ,  Jochen Beintner

IPC分类号： H01L21302

CPC分类号： H01L21/0276 ,  G03F7/091 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/3145 ,  H01L27/10861

摘要： In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

摘要翻译： 根据本发明，一种采用和去除无机抗反射涂层的方法包括以下步骤：在要加工的半导体器件结构上提供第一介电层，第一介电层可相对于半导体器件结构选择性地去除 ，并且在所述第一电介质层上形成无机介电抗反射涂层（DARC），所述DARC可相对于所述第一介电层选择性地去除。 抗蚀剂层在DARC上图案化。 抗蚀剂相对于DARC有选择性地可去除。 蚀刻半导体器件结构，并且选择性地去除抗蚀剂层，DARC和第一介电层。

公开(公告)号：US06369419B1

公开(公告)日：2002-04-09

申请号：US09603657

申请日：2000-06-23

申请人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

发明人： Ramachandra Divakaruni ,  Jochen Beintner ,  Jack A. Mandelman ,  Ulrike Gruening ,  Johann Alsmeier ,  Gary Bronner

IPC分类号： H01L2994

CPC分类号： H01L27/10867

摘要： A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The trench contains a corner adjacent the control device and the lip strap and has a conductor surrounding the corner. The control device has a control device conductive region adjacent the trench and the lip strap and has a conductor extending along a side of the trench and along a portion of the control device conductive region. In addition, the device can have a collar insulator along a top portion of the trench, wherein the lip strap includes a conductor extending from a top of the collar to a top of the trench. The lip strap can also extend along a surface of the device adjacent the trench and perpendicular to the trench. A node dielectric, lining the trench where the lip strap surrounds an upper portion of the node dielectric, is adjacent the top portion of the trench and can have a trench top oxide where the lip strap extends into the trench top oxide and forms an inverted U-shaped structure. Further, the lip strap can include a conductor extending along two perpendicular portions of a top corner of the trench.

摘要翻译： 一种用于动态随机存取存储器件的方法和结构，包括存储沟槽，存储沟槽内的存储导体，连接到存储导体的唇带，以及通过唇带电连接到存储导体的控制装置。 沟槽包含一个与控制装置和唇带相邻的拐角，并具有围绕拐角的导体。 控制装置具有与沟槽和唇缘相邻的控制装置导电区域，并且具有沿着沟槽的一侧沿着控制装置导电区域的一部分延伸的导体。 此外，该装置可以沿着沟槽的顶部具有环形绝缘体，其中，唇缘带包括从套环的顶部延伸到沟槽的顶部的导体。 唇带还可以沿邻近沟槽的表面延伸并垂直于沟槽。 衬垫在沟槽上的节点电介质，其中唇缘带围绕节点电介质的上部，与沟槽的顶部部分相邻，并且可以具有沟槽顶部氧化物，其中唇缘带延伸到沟槽顶部氧化物中并形成倒U形 形结构。 此外，唇带可以包括沿着沟槽的顶角的两个垂直部分延伸的导体。

公开(公告)号：US06204140B1

公开(公告)日：2001-03-20

申请号：US09275337

申请日：1999-03-24

申请人： Ulrike Gruening ,  Jochen Beintner ,  Scott Halle ,  Jack A. Mandelman ,  Carl J. Radens ,  Juergen Wittmann ,  Jeffrey J. Welser

发明人： Ulrike Gruening ,  Jochen Beintner ,  Scott Halle ,  Jack A. Mandelman ,  Carl J. Radens ,  Juergen Wittmann ,  Jeffrey J. Welser

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10861

摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.

摘要翻译： 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部，该凹槽在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供面罩。 掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹部底部的另一部分以暴露第二材料的下面部分。 第二材料的暴露的下部部分的部分是选择性地去除，同时留下基本未蚀刻的暴露的第一材料的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 隔离区形成在半导体本体的去除部分中。 所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分， 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法，允许更大的掩模不对准公差。

公开(公告)号：US6074903A

公开(公告)日：2000-06-13

申请号：US98203

申请日：1998-06-16

申请人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

发明人： Rajesh Rengarajan ,  Hirofumi Inoue ,  Radhika Srinivasan ,  Jochen Beintner

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L21/8238

CPC分类号： H01L21/76237

摘要： A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

摘要翻译： 一种用于在硅体中形成电绝缘的半导体器件的方法。 在身体的选定区域中形成沟槽。 阻挡材料沉积在沟槽的侧壁上。 阻挡材料的一部分从沟槽的第一侧壁部分被去除以暴露沟槽的这种第一侧壁部分，同时将这种阻挡材料的一部分留在沟槽的第二侧壁部分上以在其上形成阻挡层。 电介质材料沉积在沟槽中，介电材料的一部分沉积在暴露的沟槽的第一侧壁部分上，另一部分沉积的介电材料沉积在阻挡材料上。 电介质材料在氧化环境中退火以致密化这种淀积的介电材料，阻挡层阻止沟槽的所述第二侧壁部分的氧化。 在硅体中形成多个半导体器件，这些器件通过沟槽中的电介质材料电隔离。