公开(公告)号：US09548208B2

公开(公告)日：2017-01-17

申请号：US15045923

申请日：2016-02-17

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Nadia Vandenbroeck ,  Safak Sayan

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L29/66795

Abstract: A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising guiding structures and being substantially planar; providing a block-copolymer layer on the guiding layer; inducing phase separation of the block-copolymer layer in a regular pattern of structures of a first and a second polymer component, whereby one of the components aligns to the guiding structures, by chemo-epitaxy; thereafter, removing a first of the components of the block-copolymer layers completely, leaving a regular pattern of structures of the second component; providing a planarizing layer over the regular pattern of structures of the second component and the guiding layer; removing a portion of the planarizing layer, thereby leaving a regular pattern of structures of the planarizing layer at positions in between the structures of the second component, and exposing the structures of the second component; removing the structures of the second component, selectively with respect to the structures of the planarizing layer; and patterning the underlying layer, thereby using the structures of the planarizing layer as a mask.

Abstract translation: 描述了用于图案化下层的方法，所述方法包括在下层上提供引导层，所述引导层包括引导结构并且基本上是平面的; 在引导层上提供嵌段共聚物层; 诱导嵌段共聚物层以第一和第二聚合物组分的规则形式的结构相分离，由此其中一种组分通过化学外延对准引导结构; 此后，完全去除嵌段共聚物层中的第一组分，留下第二组分的规则的结构图案; 在所述第二部件和所述引导层的结构的规则图案上提供平坦化层; 去除所述平坦化层的一部分，从而在所述第二部件的结构之间的位置处留下所述平坦化层的规则的结构图案，并暴露所述第二部件的结构; 相对于平坦化层的结构选择性地去除第二部件的结构; 并对底层进行图案化，由此使用平坦化层的结构作为掩模。

公开(公告)号：US20160322461A1

公开(公告)日：2016-11-03

申请号：US15204853

申请日：2016-07-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Safak Sayan ,  Min-Soo Kim ,  Doni Parnell ,  Roel Gronheid

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/1037 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for producing fin structures, using Directed Self Assembly (DSA) lithographic patterning, in an area of a semiconductor substrate includes providing a semiconductor substrate covered with a shallow trench isolation (STI) layer stack on a side thereof; defining a fin area on that side of the substrate by performing a lithographic patterning step other than DSA, wherein the fin structures will be produced in the fin area; and producing the fin structures in the semiconductor substrate within the fin area according to a predetermined fin pattern using DSA lithographic patterning. The disclosure also relates to associated semiconductor structures.

公开(公告)号：US20250087643A1

公开(公告)日：2025-03-13

申请号：US18816473

申请日：2024-08-27

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Shairfe Muhammad Salahuddin

IPC: H01L25/07 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: A system includes at least two photovoltaic modules each comprising a respective module area being substantially perpendicular to the thickness of the corresponding photovoltaic module. Each of the at least two module areas comprises at least one of two first sides being substantially perpendicular to the thickness of the corresponding photovoltaic module and/or two second sides being substantially perpendicular to the thickness of the corresponding photovoltaic module. In this context, the at least two module areas are arranged in a substantially parallel manner with respect to each other and are shifted with respect to each other in an extension direction of the system. In addition to this, the at least two module areas are arranged in a staggering or alternating or ascending or descending manner with respect to an extension plane in the extension direction of the system.

公开(公告)号：US12154832B2

公开(公告)日：2024-11-26

申请号：US17504842

申请日：2021-10-19

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens

IPC: H01L21/8238 ,  H01L27/092

Abstract: According to an aspect of the present inventive concept there is provided a method for forming source/drain contacts, the method comprising: depositing a material layer over a first and second layer stack formed in a first and second device region of a substrate, respectively, each layer stack comprising a number of semiconductor channel layers and the layer stacks being separated by a trench filled with insulating material to form an insulating wall between the layer stacks and between the device regions; forming a contact partition trench in the material layer at a position above the insulating wall, and filling the contact partition trench with an insulating material to form a contact partition wall on top of the insulating wall; forming a first and a second source/drain contact trench on mutually opposite sides of the contact partition wall, the first source/drain contact trench being formed above a source/drain region in the first device region, and the second source/drain contact trench being formed above a source/drain region in the second device region, and the source/drain regions in the first and the second device region being separated by the insulating wall; and forming a first contact in the first source/drain contact trench and a second contact in the second source/drain contact trench, wherein the first and second contacts are separated by the contact partition wall.

公开(公告)号：US20240373617A1

公开(公告)日：2024-11-07

申请号：US18654367

申请日：2024-05-03

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Hsiao-Hsuan Liu ,  Boon Teik Chan ,  Shairfe Muhammad Salahuddin

IPC: H10B10/00

Abstract: A three-dimensional (3D) static random access memory (SRAM) cell includes two PU transistors arranged in a first tier, two PD transistors arranged in a second tier positioned above or below the first tier, and two PG transistors arranged in the first or second tier. The transistors can be fin transistors, and each PU and PD transistor can have a first and second number of fins, respectively. The transistors can also be nanosheet-based transistors, and each PU and PD transistor can have a first and a second nanosheet width, respectively.

公开(公告)号：US20240204081A1

公开(公告)日：2024-06-20

申请号：US18539021

申请日：2023-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Hsiao-Hsuan Liu ,  Shairfe Muhammad Salahuddin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming a semiconductor device is disclosed. The method includes: forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures; forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure; forming a dielectric plug in the cut and the opening; removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures; forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure; forming S/D contacts on the S/D structures; forming a trench for a cross-couple contact; and forming the cross-couple contact in the trench.

公开(公告)号：US20240204080A1

公开(公告)日：2024-06-20

申请号：US18538879

申请日：2023-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Hsiao-Hsuan Liu ,  Pieter Schuddinck

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.

公开(公告)号：US11854803B2

公开(公告)日：2023-12-26

申请号：US17371936

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Pierre Morin ,  Antony Premkumar Peter

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/02636 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/3212 ,  H01L21/823431 ,  H01L29/6681

Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.

公开(公告)号：US11610980B2

公开(公告)日：2023-03-21

申请号：US17210110

申请日：2021-03-23

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Changyong Xiao ,  Jie Chen

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

Abstract: A method for processing a forksheet device includes providing a substrate and forming a trench in the substrate, extending along a first direction, in the substrate. The formation of the trench includes forming a grating structure on the substrate that includes a pair of maskings, arranged at a distance from each other, and etching the trench into the substrate in a region between the pair of maskings. The method also includes filling the trench with a filling material and partially recessing the substrate to form a fin structure. This fin structure includes the filled trench, a first section of the substrate at a first side of the filled trench and a second section of the substrate at a second side of the filled trench, and forming a gate structure on and around the fin structure. The method additionally includes forming a gate structure on and around the fin structure.

公开(公告)号：US20220084822A1

公开(公告)日：2022-03-17

申请号：US17371936

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Pierre Morin ,  Antony Premkumar Peter

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/321

Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.