公开(公告)号：US20230307298A1

公开(公告)日：2023-09-28

申请号：US18205456

申请日：2023-06-02

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Eungnak HAN ,  Stephanie A. BOJARSKI ,  Florian GSTREIN ,  Gurpreet SINGH

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L21/308 ,  H01L21/02118

Abstract: Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.

公开(公告)号：US20230187395A1

公开(公告)日：2023-06-15

申请号：US17547745

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Nafees A. KABIR ,  Jeffery BIELEFELD ,  Manish CHANDHOK ,  Brennen MUELLER ,  Richard VREELAND

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L2224/08146 ,  H01L2224/05647 ,  H01L2224/02251 ,  H01L2224/0226

Abstract: Embodiments herein relate to systems, apparatuses, or processes for hybrid bonding two dies, where at least one of the dies has a top layer to be hybrid bonded includes one or more copper pad and a top oxide layer surrounding the one or more copper pad, with another layer beneath the oxide layer that includes carbon atoms. The top oxide layer and the other carbide layer beneath may form a combination gradient layer that goes from a top of the top layer that is primarily an oxide to a bottom of the other layer that is primarily a carbide. The top oxide layer may be performed by exposing the carbide layer to a plasma treatment. Other embodiments may be described and/or claimed.

公开(公告)号：US20220148967A1

公开(公告)日：2022-05-12

申请号：US17583078

申请日：2022-01-24

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Richard SCHENKER ,  Tristan TRONIC

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

公开(公告)号：US20210305358A1

公开(公告)日：2021-09-30

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210225698A1

公开(公告)日：2021-07-22

申请号：US17218080

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L23/528

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20210082800A1

公开(公告)日：2021-03-18

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200090987A1

公开(公告)日：2020-03-19

申请号：US16604681

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Sudipto NASKAR ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: Passivating silicide-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. Each of the plurality of conductive lines is recessed relative to an uppermost surface of the ILD layer. A metal silicide layer is on the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the metal silicide layer and on the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of the metal silicide layer on one of the plurality of conductive lines.

公开(公告)号：US20190237329A1

公开(公告)日：2019-08-01

申请号：US16316990

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  Florian GSTREIN ,  Manish CHANDHOK

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  C01G23/04 ,  C01F7/02 ,  C01G27/02 ,  C01G19/02

CPC classification number: H01L21/0332 ,  C01F7/00 ,  C01F7/02 ,  C01G19/02 ,  C01G23/04 ,  C01G25/02 ,  C01G27/02 ,  C01P2004/64 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

公开(公告)号：US20180204760A1

公开(公告)日：2018-07-19

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. (JZ) CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20170235228A1

公开(公告)日：2017-08-17

申请号：US15504469

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Sang H. LEE ,  Charles H. WALLACE

IPC: G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027

Abstract: Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.