公开(公告)号：US10884483B2

公开(公告)日：2021-01-05

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200310509A1

公开(公告)日：2020-10-01

申请号：US16369136

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Elkana Korem ,  Hanan Shomroni ,  Nadav Shulman

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293

Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.

公开(公告)号：US10761594B2

公开(公告)日：2020-09-01

申请号：US15623536

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/324

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20190235611A1

公开(公告)日：2019-08-01

申请号：US16382320

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/3234 ,  G06F12/0802 ,  G06F12/0864 ,  G06F1/28 ,  G06F12/084 ,  G06F1/3287 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F1/28 ,  G06F1/3287 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0848 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/502 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US09811355B2

公开(公告)日：2017-11-07

申请号：US14338692

申请日：2014-07-23

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F9/445 ,  G06F12/0844 ,  G06F13/42

CPC classification number: G06F9/44505 ,  G06F1/324 ,  G06F12/0844 ,  G06F13/4234 ,  G06F2212/1052 ,  G06F2212/604 ,  Y02D10/14 ,  Y02D10/151

Abstract: In an embodiment, a processor includes at least one core and an interconnect that couples the at least one core and the cache memory. The interconnect is to operate at an interconnect frequency (fCL). The processor also includes a power management unit (PMU) including fCL logic to determine whether to adjust the fCL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor. The Bayesian prediction value may be determined based on one or more activity measures associated with the processor. Other embodiments are described and claimed.

公开(公告)号：US20160259389A1

公开(公告)日：2016-09-08

申请号：US15157553

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有多个核心的核心域和具有第一逻辑的功率控制器，该第一逻辑接收第一请求以将核心域的第一核心的工作电压增加到第二电压，以指示电压 调节器将工作电压增加到临时电压，然后指示电压调节器将工作电压增加到第二电压。 描述和要求保护其他实施例。

公开(公告)号：US09317389B2

公开(公告)日：2016-04-19

申请号：US13931115

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Nadav Shulman ,  Shmulik Zobel ,  Allen Chu

IPC: G06F11/00 ,  G06F11/30

CPC classification number: G06F11/3024 ,  G06F11/004 ,  G06F11/008 ,  G06F11/3058

Abstract: An apparatus and method for tracking stress on a processor and responsively controlling operating conditions. For example, one embodiment of a processor comprises: stress tracking logic to determine stress experienced by one or more portions of the processor based on current operating conditions of the one or more portions of the processor; and stress control logic to control one or more operating characteristics of the processor based on the determined stress and a target stress accumulation rate.

Abstract translation: 用于跟踪处理器上的应力并响应于控制操作条件的装置和方法。 例如，处理器的一个实施例包括：应力跟踪逻辑，用于基于处理器的一个或多个部分的当前操作条件来确定处理器的一个或多个部分所经受的应力; 以及压力控制逻辑，以基于所确定的应力和目标应力累积速率来控制处理器的一个或多个操作特性。

公开(公告)号：US20160070321A1

公开(公告)日：2016-03-10

申请号：US14482148

申请日：2014-09-10

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Efraim Rotem ,  Doron Rajwan ,  Nadav Shulman ,  Esfir Natanzon ,  Nir Rosenzweig

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126

Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核和耦合到核的功率控制单元（PCU）。 PCU具有应力检测器，用于接收处理器运行的电压和温度，并计算包括有效可靠性压力在内的寿命统计信息，在诸如个人计算机，服务器计算机等计算系统的多个引导周期之后维持寿命统计信息， 平板电脑，智能电话或任何其他计算平台，基于生存期统计信息来控制处理器的一个或多个操作参数，并且经由接口将至少一部分生命周期统计信息传达给用户和/或管理实体 的处理器。 描述和要求保护其他实施例。

公开(公告)号：US20160048181A1

公开(公告)日：2016-02-18

申请号：US14461039

申请日：2014-08-15

Applicant: Intel Corporation

Inventor： Nir Rosenzweig ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman ,  Tomer Ziv

IPC: G06F1/20 ,  G06F1/32 ,  G01K13/00

CPC classification number: G06F1/206 ,  G01K1/026 ,  G01K13/00 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324

Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和多个温度传感器，其中每个核心靠近至少一个温度传感器。 该处理器还包括一个功率控制单元（PCU），其包括用于接收包括来自每个温度传感器的相应温度值的温度数据的温度逻辑。 响应于温度数据的最高温度值超过阈值的指示，温度逻辑是根据基于多个核心中的至少两个的指令执行特性的确定的策略来调整多个域频率。 每个域频率与包括多个核心中的至少一个核心的对应域相关联，并且每个域频率是可独立调整的。 描述和要求保护其他实施例。

公开(公告)号：US08775833B2

公开(公告)日：2014-07-08

申请号：US13780066

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

IPC: G06F1/00 ,  G06F15/00 ,  G05D3/12

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.