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    Program VT spread folding for NAND flash memory programming
    31.
    发明授权
    Program VT spread folding for NAND flash memory programming 有权
    用于NAND闪存编程的程序VT扩展折叠

    公开(公告)号：US09099183B2

    公开(公告)日：2015-08-04

    申请号：US14139219

    申请日：2013-12-23

    Applicant: Intel Corporation

    Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/28 ,  G11C11/56 ,  G11C16/34 ,  G11C16/08

    CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

    Abstract: Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

    Abstract translation: 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。

    NAND memory management
    32.
    发明授权
    NAND memory management 有权
    NAND内存管理

    公开(公告)号：US08943385B2

    公开(公告)日：2015-01-27

    申请号：US13658449

    申请日：2012-10-23

    Applicant: Intel Corporation

    Inventor： Ravi H. Motwani ,  Pranav Kalavade

    IPC: H03M13/05 ,  G06F11/10 ,  G06F12/02

    CPC classification number: G06F12/0246 ,  G06F11/1072 ,  G06F12/02

    Abstract: Apparatus, systems, and methods to manage NAND memory are described. In one embodiment, a memory controller logic is configured to apply a binary parity check code to a binary string and convert the binary string to a ternary string.

    Abstract translation: 描述了管理NAND存储器的装置，系统和方法。 在一个实施例中，存储器控制器逻辑被配置为将二进制奇偶校验码应用于二进制串并将二进制串转换为三进制字符串。

    CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR MEMORY DEVICES
    33.
    发明申请
    CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR MEMORY DEVICES 有权

    公开(公告)号：US20220310178A1

    公开(公告)日：2022-09-29

    申请号：US17213150

    申请日：2021-03-25

    Applicant: Intel Corporation

    Inventor： Xiang Yang ,  Ali Khakifirooz ,  Pranav Kalavade ,  Shantanu R. Rajwade

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/10

    Abstract: A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2N−1, and Ln being one of 2N threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV1.

    Defective bit line management in connection with a memory access
    34.
    发明授权
    Defective bit line management in connection with a memory access 有权

    公开(公告)号：US11429469B2

    公开(公告)日：2022-08-30

    申请号：US17195579

    申请日：2021-03-08

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Ravi H. Motwani ,  Chang Wan Ha

    IPC: G06F11/07 ,  G11C16/34 ,  G11C7/12 ,  G11C16/14 ,  G11C29/44

    Abstract: Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

    APPARATUSES, SYSTEMS, AND METHODS FOR HEATING A MEMORY DEVICE
    35.
    发明申请
    APPARATUSES, SYSTEMS, AND METHODS FOR HEATING A MEMORY DEVICE 有权

    公开(公告)号：US20210240388A1

    公开(公告)日：2021-08-05

    申请号：US16779472

    申请日：2020-01-31

    Applicant: Intel Corporation

    Inventor： Arash Hazeghi ,  Pranav Kalavade ,  Rohit Shenoy ,  Krishna Parat

    IPC: G06F3/06 ,  G05B19/406

    Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

    Segmented erase in memory
    36.
    发明授权
    Segmented erase in memory 有权

    公开(公告)号：US10453535B2

    公开(公告)日：2019-10-22

    申请号：US14922611

    申请日：2015-10-26

    Applicant: Intel Corporation

    Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

    IPC: G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/34

    Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

    Concurrent memory operations for read operation preemption
    40.
    发明授权
    Concurrent memory operations for read operation preemption 有权

    公开(公告)号：US09851905B1

    公开(公告)日：2017-12-26

    申请号：US15280898

    申请日：2016-09-29

    Applicant: INTEL CORPORATION

    Inventor： Anand S. Ramalingam ,  Pranav Kalavade ,  Aliasgar S. Madraswala

    IPC: G11C7/00 ,  G06F3/06 ,  G06F12/0802

    CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/16

    Abstract: A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.

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