公开(公告)号：US20230317583A1

公开(公告)日：2023-10-05

申请号：US17707358

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Rahul N. MANEPALLI ,  Yi YANG ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Marcel WALL

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L21/4857 ,  H05K1/181 ,  H01L24/16

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon, nitrogen, and a catalyst, and where the second layer is chemically bonded to one of the first layers.

公开(公告)号：US20220278032A1

公开(公告)日：2022-09-01

申请号：US17186289

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC: G02B6/42

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20220028788A1

公开(公告)日：2022-01-27

申请号：US17492476

申请日：2021-10-01

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20200350251A1

公开(公告)日：2020-11-05

申请号：US16931690

申请日：2020-07-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US20200266184A1

公开(公告)日：2020-08-20

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20190279935A1

公开(公告)日：2019-09-12

申请号：US16349932

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： David Allen UNRUH, JR. ,  Srinivas V. PIETAMBARAM ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/522 ,  H01L25/065 ,  H05K1/09 ,  H05K1/18 ,  H01L23/00

Abstract: Semiconductor packages including package substrates having non-homogeneous dielectric layers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package substrate includes a dielectric layer having a resin-rich region, e.g., a resin-rich sublayer, and a filler-rich region, e.g., a filler-rich sublayer. The sublayers may contain respective mixtures of an organic resin material and an inorganic filler material. The filler-rich sublayer may have a higher density of the inorganic filler material than the resin-rich sublayer. A density of the inorganic filler material may be lesser near a top surface of 0 the dielectric layer in which an electrical interconnect is embedded. The electrical interconnect may have a greater adhesion affinity to the organic resin material than the inorganic filler material, and thus, the electrical interconnect may readily attach to the functionally-graded dielectric layer.

公开(公告)号：US20150284503A1

公开(公告)日：2015-10-08

申请号：US14746750

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Dingying XU ,  Nisha ANANTHAKRISHNAN ,  Hong DONG ,  Rahul N. MANEPALLI ,  Nachiket R. RARAVIKAR ,  Gregory S. CONSTABLE

IPC: C08G59/02 ,  C07F7/08

CPC classification number: C08G59/02 ,  C07F7/0838 ,  C08G59/3254 ,  C08G59/38 ,  C08L23/0884 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3512 ,  Y10T428/31515 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Abstract translation: 描述了用于制造电子设备的底部填充材料。 一个实施方案包括含有环氧混合物，胺硬化剂组分和填料的底部填充组合物。 环氧混合物可包括包含双酚环氧树脂的第一环氧树脂，包含多官能环氧树脂的第二环氧树脂和包含脂族环氧树脂的第三环氧树脂，所述脂族环氧树脂包含硅氧烷环氧树脂。 第一，第二和第三环氧树脂各自具有不同的化学结构。 描述和要求保护其他实施例。