公开(公告)号：US09921987B2

公开(公告)日：2018-03-20

申请号：US15218727

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16 ,  G11C29/52

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US20170344512A1

公开(公告)日：2017-11-30

申请号：US15283310

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/40 ,  H04L29/08

CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4068 ,  H04L67/1095 ,  H04L69/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US09830292B2

公开(公告)日：2017-11-28

申请号：US14836234

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/40 ,  H04L12/24 ,  H04L12/917 ,  G06N99/00 ,  H04L12/911

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

公开(公告)号：US09619416B2

公开(公告)日：2017-04-11

申请号：US14667997

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US20170083079A1

公开(公告)日：2017-03-23

申请号：US15370507

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

公开(公告)号：US20160259400A1

公开(公告)日：2016-09-08

申请号：US15158271

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F1/32 ,  G06F13/42 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F9/4418 ,  G06F13/4295 ,  H04W52/0203 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D70/1222 ,  Y02D70/1226 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/166

Abstract: Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.

Abstract translation: 描述用于将端口条目同步到最低功率状态的系统，装置和方法。 在进入最低功率状态之前，端口的所有逻辑被置于中间状态。

公开(公告)号：US09262360B2

公开(公告)日：2016-02-16

申请号：US14132734

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/40 ,  H04L12/24 ,  H04L12/917 ,  H04L12/911

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

公开(公告)号：US20150370753A1

公开(公告)日：2015-12-24

申请号：US14836234

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: G06F13/42 ,  G06N99/00

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，具有链路训练状态机的设备包括重配置逻辑，以在物理链路不进入链路的运行时间内对耦合在设备和第二设备之间的物理链路进行动态链路重新配置 状态，包括向所述第二设备发送多个带宽改变请求，所述多个带宽改变请求中的每一个请求从第一带宽到第二带宽的带宽改变。 描述和要求保护其他实施例。

公开(公告)号：US09176918B2

公开(公告)日：2015-11-03

申请号：US14537859

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract translation: 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US20150220140A1

公开(公告)日：2015-08-06

申请号：US14129545

申请日：2013-04-17

Applicant: INTEL CORPORATION

Inventor： Chun Gun Por ,  Su Wei Lim

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/364 ,  G06F13/42

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F13/364 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

Abstract: Translation circuitry for facilitating communication between a protocol stack for a PCIe™ communication protocol and a PHY layer for a low power communication standard. In an embodiment, the translation circuitry includes logic is to variously convert signaling between two or more PHY interface standards. The one or more a PHY interface standards may include a PHY Interface for PCI Express (PIPE) specification and a standard for a comparatively low power communication protocol. In another embodiment, the low power communication standard is a Reference M-PHY Module Interface (RMMI) specification.

Abstract translation: 用于促进用于PCIe TM通信协议的协议栈与用于低功率通信标准的PHY层之间的通信的翻译电路。 在一个实施例中，翻译电路包括逻辑是在两个或多个PHY接口标准之间不同地转换信令。 一个或多个PHY接口标准可以包括用于PCI Express（PIPE）规范的PHY接口和用于相对低功率通信协议的标准。 在另一个实施例中，低功率通信标准是参考M-PHY模块接口（RMMI）规范。