公开(公告)号：US09985815B2

公开(公告)日：2018-05-29

申请号：US15247042

申请日：2016-08-25

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff ,  Guenther Hackl

IPC: H04L27/01 ,  H04L27/26 ,  H04L1/00

CPC classification number: H04L27/264 ,  H04L1/0038 ,  H04L25/03 ,  H04L27/2626 ,  H04L27/2644

Abstract: A signal processing device including a first signal processing chain having a first output signal; a second signal processing chain comprising a second output signal with a higher accuracy than the first output signal; a controller configured to switch, based on a desired accuracy, whether to switch between the first and second signal processing chains as a path for an original input signal; and a modifier configured to modify the original input signal, the first output signal, or the second output signal to generate a modified input, a modified first output, or a modified second output signal when the controller switches between the first and second signal processing chains.

公开(公告)号：US09832011B1

公开(公告)日：2017-11-28

申请号：US15198115

申请日：2016-06-30

Applicant: Intel IP Corporation

Inventor： Christian Wicpalek ,  Tobias Buckel ,  Andreas Menkhoff

IPC: H04L7/033 ,  H04L12/26 ,  H04L12/24 ,  H03C3/09 ,  H03L7/193 ,  H03L7/10 ,  H03L7/099 ,  H03L7/085 ,  H03L7/18 ,  H03L7/113 ,  H03L7/081 ,  H03L7/093 ,  H03L7/197 ,  H03L7/107 ,  H03L7/183 ,  H03L7/091 ,  H03L7/08 ,  H03L7/089 ,  H03L7/087 ,  H03C3/20

CPC classification number: H04L7/033 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/0991 ,  H03C3/20 ,  H03L7/08 ,  H03L7/0802 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/1075 ,  H03L7/113 ,  H03L7/18 ,  H03L7/183 ,  H03L7/193 ,  H03L7/1976 ,  H03L2207/06 ,  H03L2207/50 ,  H04L41/0681 ,  H04L43/028

Abstract: Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

公开(公告)号：US20160182100A1

公开(公告)日：2016-06-23

申请号：US14856781

申请日：2015-09-17

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff ,  Andreas Langer ,  Staffan Sahlin

IPC: H04B1/04 ,  H04W72/08 ,  H04B1/00

CPC classification number: H04B1/0475 ,  H03F1/3241 ,  H04B2001/0416 ,  H04B2001/0425 ,  H04W72/082

Abstract: A circuit for generating a radio frequency signal includes an amplifier configured to provide a radio frequency signal, the radio frequency signal being based on a baseband signal and a power supply configured to provide a variable supply voltage to the amplifier. A predistortion circuit is configured to modify the baseband signal; and a control circuit configured to control an operation mode of the predistortion circuit depending on a bandwidth of a radius of the baseband signal.

Abstract translation: 用于产生射频信号的电路包括：放大器，被配置为提供射频信号，所述射频信号基于基带信号;以及电源，被配置为向所述放大器提供可变电源电压。 预失真电路被配置为修改基带信号; 以及控制电路，被配置为根据基带信号的半径的带宽来控制预失真电路的操作模式。

公开(公告)号：US09281811B2

公开(公告)日：2016-03-08

申请号：US14546127

申请日：2014-11-18

Applicant: Intel IP Corporation

Inventor： Michael Bruennert ,  Andreas Menkhoff

IPC: H03K5/14

CPC classification number: H03K5/14

Abstract: A circuit for generating a oscillating with a selectable frequency, comprises a delay generator configured to identify a first time instant, the first time instant being delayed with respect to a signal edge of a clock signal oscillating with a predetermined clock frequency. A delay element is configured to provide a signal edge, the signal edge being delayed with respect to the first time instant such that the signal edge is provided at a second time instant corresponding to a signal edge of the synthesized signal.

Abstract translation: 用于产生具有可选频率的振荡的电路包括延迟发生器，其被配置为识别第一时刻，所述第一时刻相对于以预定时钟频率振荡的时钟信号的信号边缘被延迟。 延迟元件被配置为提供信号边缘，信号边缘相对于第一时刻被延迟，使得在对应于合成信号的信号边缘的第二时刻提供信号边缘。

公开(公告)号：US20150363362A1

公开(公告)日：2015-12-17

申请号：US14708431

申请日：2015-05-11

Applicant: Intel IP Corporation

Inventor： Andreas Menkhoff

IPC: G06F17/17 ,  H04W72/04 ,  H04L27/10

CPC classification number: H04L27/10 ,  H03C5/00 ,  H03M7/00 ,  H04L7/0029 ,  H04L27/20 ,  H04L27/361

Abstract: In a method for determining an interpolated complex valued sample, a radial component of the interpolated sample is determined using information on a radial component and information on of a phase component of a first complex valued sample and of a second complex valued sample.

Abstract translation: 在用于确定内插复值样本的方法中，使用关于径向分量的信息和关于第一复值样本和第二复值样本的相位分量的信息来确定内插样本的径向分量。