公开(公告)号：US10297598B2

公开(公告)日：2019-05-21

申请号：US15406985

申请日：2017-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul Jamison ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US10283620B2

公开(公告)日：2019-05-07

申请号：US15416281

申请日：2017-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/324 ,  H01L21/02 ,  H01L29/78

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

公开(公告)号：US10229975B2

公开(公告)日：2019-03-12

申请号：US15613930

申请日：2017-06-05

Applicant: International Business Machines Corporation

Inventor： Hemanth Jagannathan ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Koji Watanabe

IPC: H01L21/336 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/324 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.

公开(公告)号：US20190035923A1

公开(公告)日：2019-01-31

申请号：US15663133

申请日：2017-07-28

Applicant: International Business Machines Corporation

Inventor： Devendra Sadana ,  Dechao Guo ,  Joel P. de Souza ,  Ruqiang Bao ,  Stephen W. Bedell ,  Shogo Mochizuki ,  Gen Tsutsui ,  Hemanth Jagannathan ,  Marinus Hopstaken

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/02123 ,  H01L21/02304 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/762 ,  H01L29/04 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66666

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

公开(公告)号：US20180337277A1

公开(公告)日：2018-11-22

申请号：US15905891

申请日：2018-02-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：US10128372B1

公开(公告)日：2018-11-13

申请号：US15905891

申请日：2018-02-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  ChoongHyun Lee ,  Shogo Mochizuki ,  Hemanth Jagannathan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L29/0649 ,  H01L29/41741 ,  H01L29/6656 ,  H01L29/66666

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：US10096713B1

公开(公告)日：2018-10-09

申请号：US15619923

申请日：2017-06-12

Applicant: International Business Machines Corporation

Inventor： Dechao Guo ,  Hemanth Jagannathan ,  Shogo Mochizuki ,  Gen Tsutsui ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065

Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.

公开(公告)号：US20180269274A1

公开(公告)日：2018-09-20

申请号：US15805829

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kisup Chung ,  Isabel C. Estrada-Raygoza ,  Hemanth Jagannathan ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Hao Tang

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

公开(公告)号：US20180211885A1

公开(公告)日：2018-07-26

申请号：US15412499

申请日：2017-01-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/311

CPC classification number: H01L21/823857 ,  H01L21/823807 ,  H01L27/092

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.

公开(公告)号：US10002791B1

公开(公告)日：2018-06-19

申请号：US15481012

申请日：2017-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L21/823487 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.