公开(公告)号：US11282838B2

公开(公告)日：2022-03-22

申请号：US16946856

申请日：2020-07-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Dechao Guo ,  Junli Wang ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Chanro Park ,  Ruqiang Bao ,  Sung Dae Suk ,  Lan Yu ,  Heng Wu

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

公开(公告)号：US11251280B2

公开(公告)日：2022-02-15

申请号：US16717204

申请日：2019-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Lan Yu

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.

公开(公告)号：US11189725B2

公开(公告)日：2021-11-30

申请号：US16735788

申请日：2020-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Lan Yu ,  Alexander Reznicek ,  Junli Wang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.

公开(公告)号：US20210288046A1

公开(公告)日：2021-09-16

申请号：US16816372

申请日：2020-03-12

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Ruilong Xie ,  Jingyun Zhang ,  Lan Yu

IPC: H01L27/06 ,  H01L23/482 ,  H01L49/02 ,  H01L23/64

Abstract: A semiconductor device including a decoupling capacitor disposed between adjacent device source-drain regions, the decoupling capacitor comprising an outer metal liner, a dielectric disposed adjacent to the outer metal liner, and an inner metal liner disposed adjacent to the dielectric, a single diffusion break isolation region disposed between the adjacent device source-drain regions. The outer metal liner is disposed in electrical contact with the adjacent device source-drain regions.

公开(公告)号：US11094798B2

公开(公告)日：2021-08-17

申请号：US16441640

申请日：2019-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lan Yu ,  Xin Miao ,  Chen Zhang ,  Heng Wu ,  Kangguo Cheng

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/40 ,  H01L21/324 ,  H01L29/78

Abstract: An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask.

公开(公告)号：US20210159390A1

公开(公告)日：2021-05-27

申请号：US16692766

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Ruilong Xie ,  Heng Wu ,  Lan Yu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A memory structure, and a method for forming the same, includes a spin-orbit-torque electrode within a dielectric layer located above a substrate. The spin-orbit-torque electrode including a first conductive material, and a spin-orbit torque via is directly above the spin-orbit-torque electrode that includes a second conductive material. A magnetic tunnel junction pillar is directly above the spin-orbit torque via, and the spin-orbit-torque via contacting a center of a bottom surface of the magnetic-tunnel-junction pillar. A third conductive material is positioned directly below the bottom surface of the magnetic tunnel junction pillar on opposite sides of the spin-orbit torque via and directly above the spin-orbit-torque electrode. The third conductive material, the spin-orbit torque electrode and the spin-orbit torque via form a bottom spin-orbit torque electrode of the magnetic tunnel junction pillar.

公开(公告)号：US10910470B1

公开(公告)日：2021-02-02

申请号：US16515526

申请日：2019-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Alexander Reznicek ,  Lan Yu

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

公开(公告)号：US11894423B2

公开(公告)日：2024-02-06

申请号：US17677007

申请日：2022-02-22

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7851

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

公开(公告)号：US11749744B2

公开(公告)日：2023-09-05

申请号：US17341480

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Lan Yu ,  Dechao Guo ,  Junli Wang ,  Ruqiang Bao ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66666 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/0653

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom source/drain; a top source/drain; a fin provided between the bottom source/drain and the top source/drain, the fin including a first fin structure and a second fin structure that are symmetric to each other in a plan view. Each of the first and second fin structures includes a main fin extending laterally in a first direction, and first and second extension fins extending laterally from the main fin in a second direction perpendicular to the first direction. The main fin extends laterally in the first direction beyond where the first and second extension fins connect to the main fin.

公开(公告)号：US11715794B2

公开(公告)日：2023-08-01

申请号：US17464954

申请日：2021-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Ruilong Xie ,  Lan Yu ,  Alexander Reznicek ,  Junli Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66666

Abstract: Semiconductor devices include a channel fin having a top surface. A top semiconductor structure, in contact with the entire top surface of the channel fin and having a top portion and a bottom portion, with the top portion of the top semiconductor structure being narrower than the bottom portion. A restraint structure being formed over the bottom portion of the semiconductor structure.