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公开(公告)号：US09734885B1
公开(公告)日：2017-08-15
申请号：US15291127
申请日：2016-10-12
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael B. Healy , Hillery C. Hunter , Saravanan Sethuraman
CPC classification number: G11C11/1675 , G06F1/206 , G11C7/04 , G11C7/1072 , G11C11/1653 , G11C11/1673 , G11C11/1693
Abstract: A method for operating a memory system includes receiving thermal data indicating a temperature at addresses in a memory array, and a write request associate with data. An address of the write request is decoded. It is determined whether a temperature at the address of the write request is above a threshold temperature. The data is sent to a short latency write queue responsive to determining that the temperature is not above the threshold temperature.
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公开(公告)号：US09665115B2
公开(公告)日：2017-05-30
申请号：US15042751
申请日：2016-02-12
Applicant: International Business Machines Corporation
CPC classification number: G05F1/625 , G11C5/063 , G11C5/14 , G11C8/12 , H01L23/50 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: A three-dimensional (3D) integrated circuit (IC) device can include a first die having a first supply line and a second die having a second supply line, a power header, and a voltage selection logic. The power header can be connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic can be connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.
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33.发明授权Read distribution in a three-dimensional stacked memory based on thermal profiles 有权基于热剖面读取三维堆叠存储器中的分布公开(公告)号：US09575671B1
公开(公告)日：2017-02-21
申请号：US14823383
申请日：2015-08-11
Applicant: International Business Machines Corporation
IPC: G06F3/06 , G11C7/04 , G11C11/4091 , G11C11/406 , G06F9/30
CPC classification number: G06F3/0616 , G06F9/3004 , G11C7/04 , G11C11/40626 , G11C11/4091
Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.
Abstract translation: 存储器控制器可以从多个三维（3D）堆叠的存储器芯片中接收多个热分布，其中多个热分布包括用于存储器芯片的热分布数据，其中热分布数据包括存储器芯片使用 数据和每个存储器芯片的位置数据，并且其中存储器芯片包括第一存储器芯片和第二存储器芯片。 存储器控制器可以通过分析热分布数据的使用数据和位置数据来产生第一预测的存储器芯片使用数据和位置数据。 可以生成第二预测的存储器芯片使用数据和位置数据。 基于预测的存储器芯片，可以产生分数存储器芯片读取倾向数据。 存储器控制器可以根据第一分数存储器芯片读取倾向分布来分配存储器芯片读取操作。
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公开(公告)号：US09542110B2
公开(公告)日：2017-01-10
申请号：US14831127
申请日：2015-08-20
Applicant: International Business Machines Corporation
CPC classification number: G06F3/061 , G06F3/0619 , G06F3/0635 , G06F3/0644 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F11/1068 , G06F11/1666 , G06F11/2056 , G06F11/2069 , G06F11/2087 , G06F11/2094 , G06F12/1009 , G06F2201/805 , G06F2201/85 , G06F2201/86 , G11C29/44 , G11C29/52 , G11C29/70 , G11C29/76 , G11C29/886 , G11C2029/0409 , G11C2029/4402
Abstract: According to one aspect, a method for performance optimization of read functions in a memory system includes receiving, at the memory system, a read request including a logical address of a target data. The memory system includes a primary memory and a back-up memory that mirrors the primary memory. The method also includes searching a fault monitor table for an entry corresponding to the received logical address. The fault monitor table includes a plurality of entries that indicate physical locations of identified memory failure events in the primary memory and the back-up memory. Based on locating an entry corresponding to the received logical address, the method further includes selecting one of the primary memory and the backup memory for retrieving the target data. The selection is based on contents of the fault monitor table.
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公开(公告)号：US20160224079A1
公开(公告)日：2016-08-04
申请号：US14696412
申请日：2015-04-25
Applicant: International Business Machines Corporation
IPC: G06F1/20 , F24F11/053 , G05D23/19
CPC classification number: G06F1/206 , G05D23/1928 , G05D23/1932 , H05K7/20145 , H05K7/20727
Abstract: A method, system and computer program product for implementing thermal air flow control management of a computer system. A temperature profile of the server system is identified. One or more dual in-line memory-modules (DIMMs) are used to pivot on an axis to direct air flow to cool identified hot spots based upon the temperature profile of the server system.
Abstract translation: 一种用于实现计算机系统的热气流控制管理的方法，系统和计算机程序产品。 识别服务器系统的温度曲线。 基于服务器系统的温度曲线，使用一个或多个双列直插式存储器模块（DIMM）在轴上枢转以引导空气流来冷却识别的热点。
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Patent Agency Ranking
公开(公告)号：US09348744B2
公开(公告)日：2016-05-24
申请号：US14312327
申请日：2014-06-23
Applicant: International Business Machines Corporation
Inventor： Edgar R. Cordero , Carlos A. Fernandez , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
CPC classification number: G06F12/0238 , G06F11/073 , G06F11/0793 , G06F11/1044 , G06F11/1048 , G06F11/108 , G06F2212/251
Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
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公开(公告)号：US20160132408A1
公开(公告)日：2016-05-12
申请号：US14556735
申请日：2014-12-01
Applicant: International Business Machines Corporation
CPC classification number: G06F11/2058 , G06F11/1456 , G06F11/1666 , G06F11/20 , G06F11/2069 , G06F11/3037 , G06F11/3058 , G06F2201/84 , G11C5/02 , G11C7/04 , G11C29/028 , G11C29/783 , G11C29/83 , G11C2029/0409 , G11C2029/5002
Abstract: A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.
Abstract translation: 三维堆叠存储器中的镜像方法包括从多个存储器芯片接收多个热剖面图。 该方法还包括将存储器芯片的第一排列列表中的多个存储器芯片排列为多个热分布的函数，并且基于第一排列的存储芯片列表从多个存储器芯片形成第一组存储器芯片 。 该方法还包括基于第一排列的存储器芯片列表从不同于第一组存储器芯片的多个存储器芯片形成第二组存储器芯片。 该方法还包括将来自第一组存储器芯片的第一存储器芯片和来自第二组存储器芯片的第二存储器芯片配对，并且镜像存储器芯片的配对。
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公开(公告)号：US09263157B2
公开(公告)日：2016-02-16
申请号：US14138838
申请日：2013-12-23
Applicant: International Business Machines Corporation
Inventor： Charles A. Kilmer , Warren E. Maule , Saravanan Sethuraman
IPC: G11C29/50 , G11C29/00 , G11C29/02 , H01L23/538 , H01L25/065
CPC classification number: G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
Abstract translation: 公开了一种用于测试连接到并布置在用于连接缺陷的逻辑芯片的顶部上的多个存储器芯片的堆叠存储器件的方法。 该方法可以包括通过将数据值写入存储器芯片中的第一位置，从第一位置读取数据值，检测第一位错误并记录第一位错误的位数来测试存储器芯片。 该方法还可以包括通过将数据值写入存储器芯片中的第二位置来测试存储器芯片，从存储器芯片中的第二位置读取数据值，检测第二位错误并记录第二位的位数 错误。 该方法还可以包括用备用连接替换与第一和第二位错误共同的连接。
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公开(公告)号：US20150179285A1
公开(公告)日：2015-06-25
申请号：US14248480
申请日：2014-04-09
Applicant: International Business Machines Corporation
Inventor： Charles A. Kilmer , Warren E. Maule , Saravanan Sethuraman
IPC: G11C29/50 , H01L25/065 , H01L23/538 , G11C29/00
CPC classification number: G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
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公开(公告)号：US20150106569A1
公开(公告)日：2015-04-16
申请号：US14051067
申请日：2013-10-10
Applicant: International Business Machines Corporation
Inventor： Edgar R. Cordero , Anand Haridass , Subrat K. Panda , Saravanan Sethuraman , Diyanesh Babu Chinnakkonda Vidyapoornachary
IPC: G06F12/08
CPC classification number: H01L25/0657 , G06F11/00 , G06F12/0802 , H01L25/071 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.
Abstract translation: 通过将堆叠中的模具排列成使得故障核心与相邻的良好核心对齐，可以实现良好内核与故障核心缓存之间的快速连接。 可以根据分配给每个好核心的优先级，通过请求内核与可用缓存之间的延迟和/或通过核心上的负载来分配缓存。
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