公开(公告)号：US10658391B2

公开(公告)日：2020-05-19

申请号：US15381441

申请日：2016-12-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chia-Yu Chen ,  Bruce B. Doris ,  Hong He ,  Rajasekhar Venigalla

IPC: H01L27/12 ,  H01L21/30 ,  H01L21/82 ,  H01L21/84 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/04 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L21/308

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

公开(公告)号：US10170471B2

公开(公告)日：2019-01-01

申请号：US15292187

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/165

Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

公开(公告)号：US10170425B2

公开(公告)日：2019-01-01

申请号：US14538978

申请日：2014-11-12

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/44 ,  H01L21/20 ,  H01L23/532 ,  H01L21/768

Abstract: A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are described. The method of forming the metal interconnect layer includes forming an opening in a dielectric layer, forming a metal layer in the opening and over a top surface of the dielectric layer. The method also includes disposing a metal passivation layer on an overburden portion of the metal layer formed over the top surface of the dielectric layer. The metal passivation layer includes a metal selected from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy thereof, nitrides of Co, Ru, Ti, Ni, or W, and any combination thereof. The method also includes performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade.

公开(公告)号：US10164060B2

公开(公告)日：2018-12-25

申请号：US15182995

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US10020303B2

公开(公告)日：2018-07-10

申请号：US14666464

申请日：2015-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.

公开(公告)号：US09991258B2

公开(公告)日：2018-06-05

申请号：US15292768

申请日：2016-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench. The fin caps of the respective fins are separate from one another. A gate structure is formed over the fins that leaves the source and drain regions exposed. The insulator layer at least partially covers a sidewall of the gate structure.

公开(公告)号：US09917105B2

公开(公告)日：2018-03-13

申请号：US15082161

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L29/161 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/308

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

公开(公告)号：US20180061942A1

公开(公告)日：2018-03-01

申请号：US15794636

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20180061941A1

公开(公告)日：2018-03-01

申请号：US15794616

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US09881869B2

公开(公告)日：2018-01-30

申请号：US15366296

申请日：2016-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/0207 ,  H01L29/0649

Abstract: A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.