公开(公告)号：US11640942B2

公开(公告)日：2023-05-02

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11532584B2

公开(公告)日：2022-12-20

申请号：US17098754

申请日：2020-11-16

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Sri Ranga Sai Boyapati ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Javier Soto Gonzalez ,  Kwangmo Chris Lim ,  Aleksandar Aleksov

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/13 ,  H01L21/48 ,  H01L25/065

Abstract: Integrated circuit package substrates with high-density interconnect architecture for scaling high-density routing, as well as related structures, devices, and methods, are generally presented. More specifically, integrated circuit package substrates with fan out routing based on a high-density interconnect layer that may include pillars and vias, and integrated cavities for die attachment are presented. Additionally, integrated circuit package substrates with self-aligned pillars and vias formed on the high-density interconnect layer as well as related methods are presented.

公开(公告)号：US20210391263A1

公开(公告)日：2021-12-16

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11075130B2

公开(公告)日：2021-07-27

申请号：US16481216

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Lisa Ying Ying Chen ,  Lauren Ashley Link ,  Robert Alan May ,  Amruthavalli Pallavi Alur ,  Kristof Kuwawi Darmawikarta ,  Siddharth K. Alur ,  Sri Ranga Sai Boyapati ,  Andrew James Brown ,  Lilia May

IPC: H01L21/48 ,  H01L23/15 ,  C04B35/622 ,  C04B35/64 ,  H01L23/498 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.

公开(公告)号：US20190341351A1

公开(公告)日：2019-11-07

申请号：US16474026

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US12046560B2

公开(公告)日：2024-07-23

申请号：US17555222

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20240219659A1

公开(公告)日：2024-07-04

申请号：US18089871

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4239 ,  H01Q1/2283

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240096809A1

公开(公告)日：2024-03-21

申请号：US17932624

申请日：2022-09-15

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Onur Ozkan ,  Ali Lehaf ,  Steve Cho ,  Gang Duan ,  Jieping Zhang ,  Rahul N. Manepalli ,  Ravindranath Vithal Mahajan ,  Hamid Azimi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/2201 ,  H01L2224/32225

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.

公开(公告)号：US11901248B2

公开(公告)日：2024-02-13

申请号：US16832851

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Rahul N. Manepalli ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Bharat P. Penmecha

IPC: H01L23/15 ,  H01L25/065 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L25/0655

Abstract: Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.

公开(公告)号：US20220181262A1

公开(公告)日：2022-06-09

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.