公开(公告)号：US06562695B1

公开(公告)日：2003-05-13

申请号：US09889018

申请日：2001-07-10

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US06242323B1

公开(公告)日：2001-06-05

申请号：US09367524

申请日：1999-08-16

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种半导体器件，其具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤，通过减小半导体上的元件隔离槽的沟槽上边缘周围的应力产生而产生 从而优化元件隔离槽的形状并使器件更精细并提高器件的电气特性。

公开(公告)号：US5939404A

公开(公告)日：1999-08-17

申请号：US894461

申请日：1997-08-19

申请人： Shinji Iijima ,  Katsuhide Miyake ,  Shin Yamamoto ,  Yasuko Yoshida ,  Mitsuo Kawase

发明人： Shinji Iijima ,  Katsuhide Miyake ,  Shin Yamamoto ,  Yasuko Yoshida ,  Mitsuo Kawase

IPC分类号： A61K31/715 ,  A61K35/74 ,  C12P19/04 ,  A61K39/09 ,  C08B37/00

CPC分类号： C12P19/04 ,  A61K31/715

摘要： The present invention relates to the technology for inhibiting the cancer metastasis, and is aimed at the provision of a pharmaceutical composition for effectively inhibiting the metastasis of the cancer. A cancer metastasis inhibitor according to the present invention is characterized by containing a sugar chain separated from a surface of a Streptococcus agalactiae Ia type or Ib type as a main ingredient. Since the surface sugar chains of the Streptococcus agalactiae Ia type or Ib type have structures similar to surface sugar chains of the cancer cells, the former surface sugar chains adhere to E-selectin appearing in an intravascular endothelial cell, competitively inhibit the adhesion between intravascular endothelial cells and the cancer cells, and effectively prevent of the metastasis of the cancer, when the sugar chains exist in blood of a patient.

摘要翻译： PCT No.PCT / JP95 / 02735 Sec。 371日期1997年8月19日 102（e）日期1997年8月19日PCT 1995年12月27日PCT PCT。 公开号WO97 / 24130 日期：1997年7月10日本发明涉及抑制癌症转移的技术，其目的在于提供有效抑制癌症转移的药物组合物。 根据本发明的癌症转移抑制剂的特征在于含有从无乳链球菌Ia型或Ib型表面分离的糖链作为主要成分。 由于无乳链球菌Ia型或Ib型的表面糖链具有类似于癌细胞的表面糖链的结构，所以前表面糖链粘附在出现在血管内内皮细胞中的E-选择素，竞争性地抑制血管内皮细胞 细胞和癌细胞，并且当糖链存在于患者的血液中时，有效地预防癌症的转移。

公开(公告)号：US07601532B2

公开(公告)日：2009-10-13

申请号：US10947249

申请日：2004-09-23

申请人： Akira Nakagawara ,  Miki Ohira ,  Shin Ishii ,  Takeshi Goto ,  Hiroyuki Kubo ,  Takahiro Hirata ,  Yasuko Yoshida ,  Saichi Yamada

发明人： Akira Nakagawara ,  Miki Ohira ,  Shin Ishii ,  Takeshi Goto ,  Hiroyuki Kubo ,  Takahiro Hirata ,  Yasuko Yoshida ,  Saichi Yamada

IPC分类号： C12M3/00 ,  C12M1/34 ,  C07H21/02 ,  C07H21/04 ,  C12Q1/68

CPC分类号： C12Q1/6883 ,  C12Q1/6886 ,  C12Q2600/118

摘要： A microarray for predicting the prognosis of neuroblastoma, wherein the microarray has 25 to 45 probes related to good prognosis, which are hybridized to a gene transcript whose expression is increased in a good prognosis patient with neuroblastoma and are selected from 96 polynucleotides consisting of the nucleotide sequences of SEQ. ID NOs. 1, 5, 6, 14. 16, 17, 19, 22-24, 28, 29, 31, 37, 39, 40, 43, 44, 47-52, 54, 57-60, 62, 64, 65, 67, 68, 72-75, 77, 78, 80-82, 84, 87, 89-91, 94, 100, 103, 112, 113, 118, 120, 129, 130, 132, 136, 138, 142, 144, 145, 148, 150-153, 155, 158-160, 163-165, 169-171, 173, 174, 177, 178, 180-182, 184, 186, 187, 189, 191, 192, 194, 195, 198-200 or their partial continuous sequences or their complementary strands, and 25 to 45 probes related to poor prognosis, which are hybridized to a gene transcript whose expression is increased in a poor prognosis patient with neuroblastoma and are selected from 104 polynucleotides consisting of the nucleotide sequences of SEQ. ID NOs. 2-4, 7-13, 15, 18, 20, 21, 25-27, 30, 32-36, 38, 41, 42, 45, 46, 53, 55, 56, 61, 63, 66, 69-71, 76, 79, 83, 85, 86, 88, 92, 93, 95-99, 101, 102, 104-111, 114-117, 119, 121-128, 131, 133-135, 137, 139-141, 143, 146, 147, 149, 154, 156, 157, 161, 162, 166-168, 172, 175, 176, 179, 183, 185, 188, 190, 193, 196, 197 or their partial continuous sequences or their complementary strands.

摘要翻译： 一种用于预测神经母细胞瘤的预后的微阵列，其中所述微阵列具有与良好预后相关的25至45个探针，其与在具有神经母细胞瘤的良好预后患者中表达增加的基因转录物杂交，并且选自96个由核苷酸 SEQ。 身份证号 1，5，6，14，16，17，19，22-24，28，29，31，37，39，40，43，44，47-52，54，57-60，62，64，65， 67，68，72-75，77，78，80-82，84，87，89-91，94，100，103，112，113，118，120，129，130，132，136，138， 144,145,148,150-153,155,158-160,163-165,169-171,173,174,177,178,180-182,184,186,187,189,191,192,194， 195，198-200或其部分连续序列或其互补链，以及与不良预后相关的25至45个探针，其与在具有神经母细胞瘤的不良预后患者中表达增加的基因转录物杂交，并且选自104个多核苷酸 的SEQ ID NO： 身份证号 2-4，7-13，15，18，20，21，25-27，30，32-36，38，41，42，45，46，53，55，56，61，63，66，69- 71,76,79,83,85,86,88,92,93,95-99,101,102,104-111,114-117,119,121-128,131,133-135,137,139- 141,143,146,147,149,154,156,157,161,162,166-168,172,175,176,179,183,185,188,190,193,196,197或其部分连续序列 或其互补链。

公开(公告)号：US07488639B2

公开(公告)日：2009-02-10

申请号：US11342695

申请日：2006-01-31

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L21/8238

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

公开(公告)号：US20080240946A1

公开(公告)日：2008-10-02

申请号：US12149822

申请日：2008-05-08

申请人： Toshikazu Hirota ,  Yasuko Yoshida

发明人： Toshikazu Hirota ,  Yasuko Yoshida

IPC分类号： F04B17/00

CPC分类号： G01N27/44704 ,  B01F11/02 ,  B01F13/0059 ,  B01L3/50273 ,  B01L3/502738 ,  B01L3/502746 ,  B01L2300/0816 ,  B01L2300/0867 ,  B01L2300/1827 ,  B01L2400/0421 ,  B01L2400/0439 ,  B01L2400/0605 ,  B01L2400/0677 ,  B01L2400/082 ,  F04B43/043 ,  F04B53/1077 ,  G01N27/44791

摘要： A microchemical chip comprises a plate-shaped substrate, with a channel formed on a surface of the substrate through which a fluid flows. A fluid storage section for storing the fluid communicates with the channel at a starting end of the channel. A fluid discharge section communicates with the channel at a terminal end of the channel. An extruding pump section is formed integrally on the substrate, at a portion of the channel in the vicinity of the fluid storage section.

摘要翻译： 微化学芯片包括板状基板，其中通道形成在基板的表面上，流体流过该基板。 用于存储流体的流体存储部分在通道的起始端与通道连通。 流体排放部分在通道的末端与通道连通。 挤压泵部分在流体存储部分附近的通道的一部分处一体地形成在基板上。

公开(公告)号：US20080142901A1

公开(公告)日：2008-06-19

申请号：US12028593

申请日：2008-02-08

申请人： Shuji MATSUO ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

发明人： Shuji MATSUO ,  Katsuhiro Uchimura ,  Yasuko Yoshida ,  Kota Funayama ,  Yutaka Takeshima

IPC分类号： H01L27/088

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

摘要： A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSi2 layer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

摘要翻译： 半导体器件的制造方法包括在半导体衬底上形成栅极绝缘膜和由多晶硅制成的栅电极; 将离子注入到半导体衬底中以形成作为源极或漏极的半导体区域; 在所述半导体衬底上形成钴膜和氮化钛膜以覆盖所述栅电极; 进行退火以引起Co和Si之间的反应以及半导体区域以形成CoSi层; 进行湿式清洗以除去氮化钛膜和未反应的钴膜，使CoSi层离开栅电极和半导体区域; 进行退火以引起CoSi层与栅极电极和半导体区域之间的反应以形成CoSi 2层; 进行HPM清洗; 以及通过低压CVD在半导体衬底上形成氮化硅膜以覆盖栅电极。

公开(公告)号：US07200254B2

公开(公告)日：2007-04-03

申请号：US10235999

申请日：2002-09-05

申请人： Shigeki Kira ,  Kazunari Yamada ,  Toshikazu Hirota ,  Yasuko Yoshida

发明人： Shigeki Kira ,  Kazunari Yamada ,  Toshikazu Hirota ,  Yasuko Yoshida

IPC分类号： G06K9/00 ,  G06K9/32

CPC分类号： B82Y30/00 ,  B01J19/0046 ,  B01J2219/00529 ,  B01J2219/0054 ,  B01J2219/00576 ,  B01J2219/00677 ,  B01J2219/00689 ,  B01J2219/00693 ,  B01J2219/00695 ,  B01J2219/00702 ,  B01J2219/00722 ,  C40B40/06 ,  G01N2035/00158 ,  G01N2035/0494

摘要： Technology is disclosed for highly accurate automated execution of processing for alignment of a detection area to a DNA microarray image file and processing for quantitative determination of success/failure of the alignment during DNA microarray analysis. A probe reactive chip used for the technology comprises a substrate; a spot region wherein spots for fixing a probe capable of specifically reacting to a sample marked so as to be optically detectable are formed in a matrix on a surface of the substrate; and a reference pattern area, which is arranged within the spot region or approximate to the spot region, and comprises a plurality of different alignment marks in order to correct misalignment of the spot during analysis of the sample on the surface of the substrate.

摘要翻译： 公开了用于高精度自动执行用于将检测区域与DNA微阵列图像文件对齐的处理的技术，以及用于在DNA微阵列分析期间定量确定取向成功/失败的处理。 用于该技术的探针反应性芯片包括基底; 斑点区域，其中用于固定探针的斑点能够与标记为可光学检测的样品特异性反应，形成在基底表面上的基质中; 以及布置在斑点区域内或近似于斑点区域的参考图案区域，并且包括多个不同的对准标记，以便在基底表面上的样品分析期间校正斑点的未对准。

公开(公告)号：US07088001B2

公开(公告)日：2006-08-08

申请号：US10844479

申请日：2004-05-13

申请人： Hiroshi Ashihara ,  Tatsuyuki Saito ,  Uitsu Tanaka ,  Hidenori Suzuki ,  Hideaki Tsugane ,  Yasuko Yoshida ,  Ken Okutani

发明人： Hiroshi Ashihara ,  Tatsuyuki Saito ,  Uitsu Tanaka ,  Hidenori Suzuki ,  Hideaki Tsugane ,  Yasuko Yoshida ,  Ken Okutani

IPC分类号： H01L23/48

CPC分类号： H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76877 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to form a good contact between metallizations and improve the reliability and product yield of a semiconductor integrated circuit device, a plug is formed in a contact hole by depositing a first sputter film inside of the contact hole by traditional sputtering, depositing a second sputter film over the first sputter film by long throw sputtering, depositing a W film over the second sputtering film by CVD and removing the first and second sputter films and the W film from the outside of the contact hole. The barrier properties can be improved by constituting a barrier film from the first sputter film and second sputter film which are different in directivity.

摘要翻译： 为了在金属化之间形成良好的接触并提高半导体集成电路器件的可靠性和产品产量，通过传统溅射在接触孔内部沉积第一溅射膜，在接触孔中形成插塞，沉积第二溅射 通过长溅射溅射第一溅射膜上的膜，通过CVD在第二溅射膜上沉积W膜，并从接触孔的外部除去第一和第二溅射膜和W膜。 可以通过从方向性不同的第一溅射膜和第二溅射膜构成阻挡膜来改善阻挡性。

公开(公告)号：US07067864B2

公开(公告)日：2006-06-27

申请号：US10363055

申请日：2001-12-26

申请人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

发明人： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

摘要翻译： 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。