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89 条记录 (耗时 0.027 秒)

    Undercut insulating regions for silicon-on-insulator device
    31.
    发明授权
    Undercut insulating regions for silicon-on-insulator device 有权
    用于绝缘体上硅器件的底切绝缘区域

    公开(公告)号：US09214378B2

    公开(公告)日：2015-12-15

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
    32.
    发明申请
    ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS 有权
    用于薄盒ETSOI MOSFET的稳定隔离

    公开(公告)号：US20130264641A1

    公开(公告)日：2013-10-10

    申请号：US13442168

    申请日：2012-04-09

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

    摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

    摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

    Method to form low series resistance transistor devices on silicon on insulator layer
    33.
    发明授权
    Method to form low series resistance transistor devices on silicon on insulator layer 有权
    在绝缘体硅层上形成低串联电阻晶体管器件的方法

    公开(公告)号：US08440552B1

    公开(公告)日：2013-05-14

    申请号：US13346008

    申请日：2012-01-09

    申请人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

    发明人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

    IPC分类号： H01L21/225

    CPC分类号： H01L21/2255 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636

    摘要： A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.

    摘要翻译： 一种方法包括提供具有半导体层的ETSOI晶片，所述半导体层具有顶表面，所述半导体层具有至少一个在其侧壁上具有介电材料层的栅极结构。 电介质材料层的一部分远离半导体层表面上的栅极结构延伸。 该方法还包括将邻近该介电材料层的部分的半导体层上的升高的S / D断开，去除介电材料层的该部分以暴露该半导体层表面的下面部分并施加一层 的含有掺杂剂的玻璃以至少覆盖半导体层的表面的暴露部分。 该方法还包括通过半导体层的表面的暴露部分扩散掺杂剂以形成源极延伸区域和漏极延伸区域。

    DEVICE WITH STRESSED CHANNEL
    35.
    发明申请
    DEVICE WITH STRESSED CHANNEL 审中-公开
    具有应力通道的设备

    公开(公告)号：US20110031503A1

    公开(公告)日：2011-02-10

    申请号：US12538627

    申请日：2009-08-10

    申请人： Bruce B. Doris ,  Johnathan E. Faltermeier ,  Lahir S. Adam ,  Balasubramanian S. Haran

    发明人： Bruce B. Doris ,  Johnathan E. Faltermeier ,  Lahir S. Adam ,  Balasubramanian S. Haran

    IPC分类号： H01L29/161 ,  H01L27/092 ,  H01L21/04 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.

    摘要翻译： 公开了一种FET器件，其包含各自具有延伸部的源极和漏极。 源极和漏极及其延伸部分由包含Ge或C的外延材料组成。外延材料和Si衬底具有不同的晶格常数，因此源极和漏极及其延伸部分在沟道上赋予应力状态 。 对于PFET器件，外延材料可以是SiGe或Ge，并且沟道可以处于压应力的压缩状态。 对于NFET器件，外延材料可以是SiC，并且沟道可以处于应力的拉伸状态。 还公开了一种用于制造FET器件的方法。 可以在Si衬底中形成第一凹陷到栅极的相对侧上的第一深度。 用第一外延材料外延地填充第一次衰退。 然后，可以在Si衬底中形成比第一深度更大的第二深度的第二凹陷。 接下来，可以用与第一外延材料相同的材料的第二外延材料填充第二凹陷。 选择外延材料具有与Si衬底不同的晶格常数，并且因此在沟道上施加应力状态。

    MOSFET including asymmetric source and drain regions
    37.
    发明授权
    MOSFET including asymmetric source and drain regions 失效
    MOSFET包括不对称的源极和漏极区域

    公开(公告)号：US08772874B2

    公开(公告)日：2014-07-08

    申请号：US13216554

    申请日：2011-08-24

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS
    38.
    发明申请
    SOI DEVICE WITH EMBEDDED LINER IN BOX LAYER TO LIMIT STI RECESS 有权
    具有嵌入式衬垫的SOI器件限制STI感染

    公开(公告)号：US20140070357A1

    公开(公告)日：2014-03-13

    申请号：US13611182

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L27/1203 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66772 ,  H01L29/78654

    摘要： A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

    摘要翻译： 具有隔离区域的半导体基板及其形成方法。 该方法包括以下步骤：提供具有衬底层，掩埋氧化物（BOX），绝缘体上硅（SOI）层，衬垫氧化物层和衬垫氮化物层的衬底，形成浅沟槽区，蚀刻衬垫 氧化层以形成耳朵并蚀刻BOX层以形成底切，在浅沟槽区域上沉积衬垫，在浅沟槽区域的表面上沉积软掩模，填充浅沟槽区域，蚀刻软掩模，使得它 凹陷到BOX层的顶部，在某些区域蚀刻衬垫，去除软掩模，以及填充和抛光浅沟槽区域。 当触点不对准时，衬垫防止半导体器件的短路。