公开(公告)号：US6031288A

公开(公告)日：2000-02-29

申请号：US747392

申请日：1996-11-12

申请人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

发明人： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L29/7845 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

摘要翻译： 半导体器件包括硅衬底，电布线金属，形成在硅衬底上的绝缘膜，形成在用于将硅衬底和电布线金属彼此连接的绝缘膜中的多个接触孔，以及硅化钛 膜在接触孔中形成。 硅化钛膜的厚度为10nm〜120nm，优选为20nm〜84nm。 半导体区域和电布线金属通过硅化钛膜彼此连接。

公开(公告)号：US08034715B2

公开(公告)日：2011-10-11

申请号：US12492276

申请日：2009-06-26

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/44 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US20070184603A1

公开(公告)日：2007-08-09

申请号：US11783187

申请日：2007-04-06

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

摘要翻译： 在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

公开(公告)号：US20050118805A1

公开(公告)日：2005-06-02

申请号：US11006702

申请日：2004-12-08

申请人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

发明人： Shinji Nishihara ,  Shuji Ikeda ,  Naotaka Hashimoto ,  Hiroshi Momiji ,  Hiromi Abe ,  Shinichi Fukada ,  Masayuki Suzuki

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/532 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/823814 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/31608 ,  H01L21/76229 ,  H01L21/76828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/53223 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

公开(公告)号：US5543652A

公开(公告)日：1996-08-06

申请号：US98893

申请日：1993-07-29

申请人： Shuji Ikeda ,  Makoto Saeki

发明人： Shuji Ikeda ,  Makoto Saeki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/88 ,  H01L27/01 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

摘要： Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.

摘要翻译： 具有相同沟道导电类型且具有不同阈值电压的负特性MISFET形成在沉积在衬底上并以通道间通道串联连接的掺杂硅薄膜中。 一对串联负特性MISFET，电阻元件，信息存储电容元件和转移MISFET构成SRAM存储单元。 等效地，可以使用由负电阻曲线限定的电流 - 电压特性的负特性MISFET来代替在SRAM的各个存储单元的形成中的一对串联负特性MISFET。 负特性MISFET的负电阻曲线被成形为使得对应于存储单元的电阻元件的线性电流 - 电压特性曲线在至少三个位置点处与负电阻曲线相交。 负极特性MISFET，像一对串联连接的负特性MISFET一样，具有在衬底主表面上绝缘的掺杂薄膜硅（多晶硅）层中形成的有源区。 电阻元件也与负特性MISFET或单独的薄膜硅层整体地形成在薄膜硅层中，并与负特性MISFET串联电连接。

公开(公告)号：US5055420A

公开(公告)日：1991-10-08

申请号：US351323

申请日：1989-05-09

申请人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L21/823814 ,  H01L29/0847 ,  H01L27/0928

摘要： After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to fornm an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

公开(公告)号：US4734383A

公开(公告)日：1988-03-29

申请号：US800954

申请日：1985-11-22

申请人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

发明人： Shuji Ikeda ,  Kouichi Nagasawa ,  Makoto Motoyoshi ,  Kiyoshi Nagai ,  Satoshi Meguro

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L29/0847 ,  H01L27/0928

摘要： After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

摘要翻译： 在P和N沟道MOSFET的P型和N型源极区或漏极区的接触孔已经制成了共同的步骤之后，N型杂质被离子注入至少N型源极或漏极 区域通过接触孔。 将N型杂质退火，形成比N型源区或漏区更深的N型区。 在退火处理期间，N型源极或漏极区域被绝缘膜覆盖。

公开(公告)号：US09499576B2

公开(公告)日：2016-11-22

申请号：US13997700

申请日：2011-12-28

申请人： Akimitsu Okamoto ,  Shuji Ikeda

发明人： Akimitsu Okamoto ,  Shuji Ikeda

IPC分类号： C07H21/04 ,  C07H21/00 ,  C07H19/10 ,  C07H19/048 ,  C07H19/073

CPC分类号： C07H19/10 ,  C07H19/073 ,  C07H21/04

摘要： The present invention relates to a compound represented by Formulas 1, 2 or 3 as described herein, and a nucleic acid each of which contains a dye exhibiting an exciton effect, a method of producing such a nucleic acid by using the compound, and a kit for producing the nucleic acid.

摘要翻译： 本发明涉及本文所述的由式1,2或3表示的化合物，以及含有表现出激子作用的染料的核酸，通过使用该化合物制备该核酸的方法和试剂盒 用于产生核酸。

公开(公告)号：US20140045183A1

公开(公告)日：2014-02-13

申请号：US14111825

申请日：2012-04-16

申请人： Akimitsu Okamoto ,  Kaori Sugizaki ,  Akiko Nakamura ,  Hiroyuki Yanagisawa ,  Shuji Ikeda

发明人： Akimitsu Okamoto ,  Kaori Sugizaki ,  Akiko Nakamura ,  Hiroyuki Yanagisawa ,  Shuji Ikeda

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6806 ,  C12Q1/6827 ,  C12Q1/6858 ,  Y10T436/143333 ,  C12Q2523/115 ,  C12Q2537/164

摘要： Provided are a method and a kit for detecting 5-hydroxymethylcytosine in a nucleic acid. The method is a method for detecting 5-hydroxymethylcytosine in a nucleic acid, comprising the steps of: (1) oxidizing 5-hydroxymethylcytosine in a nucleic acid sample by treating the nucleic acid sample with a tungstic acid-based oxidizing agent comprising peroxotungstic acid, tungstic acid, a salt thereof, or a combination thereof with a reoxidizing agent; and (2) determining the position of the oxidized 5-hydroxymethylcytosine in the nucleic acid sample.

摘要翻译： 提供了用于检测核酸中5-羟甲基胞嘧啶的方法和试剂盒。 该方法是用于检测核酸中5-羟甲基胞嘧啶的方法，其包括以下步骤：（1）通过用包含过氧钨酸的钨酸氧化剂处理核酸样品来氧化核酸样品中的5-羟甲基胞嘧啶， 钨酸，其盐或其与再氧化剂的组合; 和（2）确定核酸样品中氧化的5-羟甲基胞嘧啶的位置。

公开(公告)号：US20110012181A1

公开(公告)日：2011-01-20

申请号：US12890431

申请日：2010-09-24

申请人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka HASHIMOTO ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L27/108 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。