公开(公告)号：US08735276B2

公开(公告)日：2014-05-27

申请号：US13365378

申请日：2012-02-03

申请人： Hyun-Soo Chung ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

发明人： Hyun-Soo Chung ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC分类号： H01L21/768

CPC分类号： H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20120261821A1

公开(公告)日：2012-10-18

申请号：US13537953

申请日：2012-06-29

申请人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC分类号： H01L23/488

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

公开(公告)号：US20110242655A1

公开(公告)日：2011-10-06

申请号：US13078797

申请日：2011-04-01

申请人： Ji-Woon Jung ,  Dong-Ho Lee ,  Seon-Chool Kim ,  Jong-Kap Jo ,  Sang-Kyu Kim

发明人： Ji-Woon Jung ,  Dong-Ho Lee ,  Seon-Chool Kim ,  Jong-Kap Jo ,  Sang-Kyu Kim

IPC分类号： G02B5/30

CPC分类号： G02B5/3033 ,  G02B5/3025 ,  G02F1/13338

摘要： A flat panel display apparatus is disclosed. In one embodiment, the apparatus includes a panel configured to display an image; a glass window covering the panel; and a polarizing film attached on a surface of the glass window, wherein the polarizing film is configured to prevent the scatter of broken pieces when the glass window breaks and also prevent reflection of an external light.

摘要翻译： 公开了一种平板显示装置。 在一个实施例中，该装置包括被配置为显示图像的面板; 覆盖面板的玻璃窗; 以及偏振膜，其安装在所述玻璃窗的表面上，其中，所述偏振膜被构造成在所述玻璃窗断裂时防止碎片的散射，并且还防止外部光的反射。

公开(公告)号：US07884875B2

公开(公告)日：2011-02-08

申请号：US11866940

申请日：2007-10-03

申请人： Yong-Chai Kwon ,  Dong-Ho Lee

发明人： Yong-Chai Kwon ,  Dong-Ho Lee

IPC分类号： H04N5/225 ,  H01L21/00

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

摘要翻译： 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US07847383B2

公开(公告)日：2010-12-07

申请号：US11797592

申请日：2007-05-04

申请人： Byung-Se So ,  Dong-Ho Lee

发明人： Byung-Se So ,  Dong-Ho Lee

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

摘要翻译： 多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/​​输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。 第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。 第一半导体芯片的输入/输出焊盘通过多芯片封装的相应引脚直接接收输入/输出信号。 第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。 当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。

公开(公告)号：US07843053B2

公开(公告)日：2010-11-30

申请号：US12338905

申请日：2008-12-18

申请人： Dong-Ho Lee

发明人： Dong-Ho Lee

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/15311

摘要： A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

摘要翻译： 通过堆叠至少两个区域阵列型芯片级封装件来制造本发明的堆叠封装。 相邻的一对芯片级封装的每个芯片级封装以上堆叠芯片级封装的焊盘焊盘与下堆叠芯片尺寸封装的方向相反的方式附接到另一芯片尺寸封装，并且电路 上堆叠芯片级封装的图案通过例如连接板电连接到下堆叠芯片级封装的图案。 因此，不仅可以堆叠扇出式芯片级封装，而且可以有效地堆叠普通区域阵列型芯片级封装。

公开(公告)号：US07838992B2

公开(公告)日：2010-11-23

申请号：US12496176

申请日：2009-07-01

申请人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

发明人： Hyun-Soo Chung ,  Ho-Jin Lee ,  Dong-Hyun Jang ,  Dong-Ho Lee

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/274 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/01087

摘要： In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

摘要翻译： 在具有应力消除间隔物的半导体器件封装及其制造方法中，从芯片本体延伸的金属互连指状物提供芯片互连。 金属手指通过应力消除间隔物与芯片的主体隔离。 在一个示例中，这种隔离采取气隙的形式。 在另一个实例中，这种隔离采用弹性体材料的形式。 在这两种情况下，都避免了金属互连指和芯体之间的热膨胀系数的不匹配，从而减轻了与开裂和分层相关的问题，从而提高了器件的产量和器件的可靠性。

公开(公告)号：US07777323B2

公开(公告)日：2010-08-17

申请号：US11750663

申请日：2007-05-18

申请人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

发明人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

IPC分类号： H01L23/12 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

摘要： Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

摘要翻译： 示例性实施例涉及一种形成半导体结构的方法和包括半导体单元的半导体结构的方法，所述半导体单元包括在半导体单元的前侧上的突起和半导体单元的背侧上的凹部。

公开(公告)号：US20100032807A1

公开(公告)日：2010-02-11

申请号：US12588231

申请日：2009-10-08

申请人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC分类号： H01L23/544

CPC分类号： H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

摘要翻译： 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US07626260B2

公开(公告)日：2009-12-01

申请号：US11751464

申请日：2007-05-21

申请人： Hyun-Soo Chung ,  Cha-Jea Jo ,  Dong-Ho Lee ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Cha-Jea Jo ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC分类号： H01L23/34

CPC分类号： H01L23/473 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

摘要： Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.

摘要翻译： 提供了在其底面上具有冷却路径的半导体器件。 具有冷却路径的叠层型半导体器件包括：堆叠型半导体芯片，包括第一半导体芯片和第二半导体芯片。 第一半导体芯片包括其中形成有电路单元的第一表面和形成有第一冷却路径的第二表面，并且第二半导体芯片包括其中形成电路单元的第一表面和第二表面，其中第二表面 形成第二冷却路径。 第一半导体芯片的第二表面和第二半导体芯片的第二表面彼此接合，并且使用第一和第二冷却路径在堆叠型半导体芯片的中间形成第三冷却路径。 堆叠型半导体器件的翘曲被抑制，并且易于散热。