公开(公告)号：US20240072024A1

公开(公告)日：2024-02-29

申请号：US17897156

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/35121

Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.

公开(公告)号：US20240047423A1

公开(公告)日：2024-02-08

申请号：US17879660

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L21/304

CPC classification number: H01L25/0657 ,  H01L21/3043 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2924/10158 ,  H01L24/48

Abstract: A semiconductor device assembly is provided. The assembly includes an outer semiconductor device which has an active surface and a back surface. The back surface includes a cut that extends to a depth between the active surface and the back surface, and uncut regions on opposing sides of the cut. The assembly further includes an inner semiconductor device disposed within the cut of the outer semiconductor device.

公开(公告)号：US20230378043A1

公开(公告)日：2023-11-23

申请号：US17750140

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846

Abstract: Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.

公开(公告)号：US11723150B2

公开(公告)日：2023-08-08

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/642 ,  H01L25/0657 ,  H05K1/181 ,  H01L23/49816 ,  H05K2201/10015 ,  H05K2201/10159

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US11527459B2

公开(公告)日：2022-12-13

申请号：US17243466

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20220078915A1

公开(公告)日：2022-03-10

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US11189548B2

公开(公告)日：2021-11-30

申请号：US15627076

申请日：2017-06-19

Applicant: Micron Technology, Inc.

Inventor： Ai-Chie Wang ,  Choon Kuan Lee ,  Chin Hui Chong ,  Wuu Yean Tay

IPC: H01L23/495 ,  H01L23/00

Abstract: Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.

公开(公告)号：US10211114B2

公开(公告)日：2019-02-19

申请号：US15702225

申请日：2017-09-12

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC: H01L23/053 ,  H01L25/065 ,  H01L25/11 ,  H01L23/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/66

Abstract: Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate.

公开(公告)号：US09355992B2

公开(公告)日：2016-05-31

申请号：US14450998

申请日：2014-08-04

Applicant: Micron Technology, Inc.

Inventor： Lee Choon Kuan ,  David J. Corisis ,  Chin Hui Chong

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/92 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/49531 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads on the same side of the interposer substrate as the at least one semiconductor die. Terminal pads of the interposer substrate may be electrically connected to either or both of a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. Additional components, active, passive or both, may be connected to pads of the two-dimensional array to provide a system-in-a-package. Lead fingers of a lead frame may be superimposed on the opposing side of the interposer substrate, bonded directly to the land grid array land and wire bonded to pads as desired for repair or to ease routing problems on the interposer. The land grid array package may be mounted to a carrier substrate, and the lands wire bonded to conductive pads on the carrier substrate. Methods of fabrication are also disclosed.

Abstract translation: 半导体器件封装包括焊盘栅格阵列封装。 至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到与至少一个半导体管芯在内插器衬底的同一侧上的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案中的一个或两个以及中心的二维阵列阵列图案，两个阵列图案位于至少从中间层基板的相对侧起至少 一个半导体芯片。 可以将主动，被动或两者的附加组件连接到二维阵列的焊盘以提供系统级封装。 引线框架的引脚可以叠置在插入器基板的相对侧上，直接接合到焊盘栅格阵列焊盘，并且焊接到焊盘上，以便修理或者简化插入器上的布线问题。 焊盘阵列封装可以安装到载体衬底上，焊盘引线键合到载体衬底上的导电焊盘上。 还公开了制造方法。

公开(公告)号：US09084360B2

公开(公告)日：2015-07-14

申请号：US13866713

申请日：2013-04-19

Applicant: Micron Technology, Inc.

Inventor： David J. Corisis ,  Choon Kuan Lee ,  Chin Hui Chong

IPC: H05K1/11 ,  G01R31/02 ,  H05K1/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  G06F1/16 ,  H05K1/18 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract translation: 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。