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    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
    31.
    发明授权
    Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal 有权

    公开(公告)号：US10515676B2

    公开(公告)日：2019-12-24

    申请号：US16143082

    申请日：2018-09-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076

    Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

    APPARATUSES AND METHODS FOR DUTY CYCLE ERROR CORRECTION OF CLOCK SIGNALS
    32.
    发明申请
    APPARATUSES AND METHODS FOR DUTY CYCLE ERROR CORRECTION OF CLOCK SIGNALS 审中-公开

    公开(公告)号：US20190198075A1

    公开(公告)日：2019-06-27

    申请号：US15853514

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

    IPC: G11C8/18 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32

    CPC classification number: G11C8/18 ,  G11C7/222 ,  G11C16/08 ,  G11C16/28 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028

    Abstract: Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.

    Method and apparatus for memory command input and control
    34.
    发明授权
    Method and apparatus for memory command input and control 有权
    用于存储器命令输入和控制的方法和装置

    公开(公告)号：US09466348B2

    公开(公告)日：2016-10-11

    申请号：US14565822

    申请日：2014-12-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

    IPC: G11C7/00 ,  G11C8/12 ,  G11C7/10 ,  G06F13/42

    CPC classification number: G11C8/12 ,  G06F13/4234 ,  G11C7/00 ,  G11C7/10 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

    Abstract translation: 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 具有控制逻辑的芯片使能电路被配置为接收芯片选择信号，并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。

    Bank-level self-refresh
    36.
    发明授权
    Bank-level self-refresh 有权

    公开(公告)号：US12300300B2

    公开(公告)日：2025-05-13

    申请号：US17660199

    申请日：2022-04-21

    Applicant: Micron Technology, Inc.

    Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

    IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4076

    Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

    Bus training with interconnected dice
    37.
    发明授权
    Bus training with interconnected dice 有权

    公开(公告)号：US12235783B2

    公开(公告)日：2025-02-25

    申请号：US17823415

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Francesco Douglas Verna-Ketel ,  Hyun Yoo Lee ,  Smruti Subhash Jhaveri ,  John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim

    IPC: G06F13/40 ,  G06F13/16

    Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

    APPARATUSES AND METHODS FOR MULTIPLE TYPES OF ALERT ALONG ALERT BUS
    38.
    发明申请
    APPARATUSES AND METHODS FOR MULTIPLE TYPES OF ALERT ALONG ALERT BUS 有权

    公开(公告)号：US20240428842A1

    公开(公告)日：2024-12-26

    申请号：US18743309

    申请日：2024-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Randall J. Rooney ,  David R. Brown ,  Michael A. Shore ,  Kang-Yong Kim

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: Apparatuses, systems, and methods for multiple types of alert along an alert bus. A memory device may detect multiple types of alert and use an alert signal along an alert bus to signal a controller of these alerts. Different pulse widths of the alert signal may be used to indicate the type of alert. For example if the alert signal is at an active level between a first duration and a second duration, it may indicate a first type of alert, if the alert signal is active between a third duration and a fourth duration, it may indicate a second type of alert. If the alert signal remains active for longer than a threshold amount of time, it may indicate a third type of alert.

    Internal and external data transfer for stacked memory dies
    39.
    发明授权
    Internal and external data transfer for stacked memory dies 有权

    公开(公告)号：US12176059B2

    公开(公告)日：2024-12-24

    申请号：US18407062

    申请日：2024-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyunyoo Lee

    IPC: G11C7/10

    Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

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